Simulation Results: chip

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 68.65 %
  • code
  • 83.94 %
  • assert
  • 97.37 %
  • func
  • 24.65 %
  • line
  • 94.05 %
  • branch
  • 92.51 %
  • cond
  • 87.48 %
  • toggle
  • 88.54 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.90%
V2S
100.00%
V3
69.23%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 152.310s 3180.381us 1 1 100.00
chip_sw_example_rom 84.100s 2532.186us 1 1 100.00
chip_sw_example_manufacturer 147.890s 2229.084us 1 1 100.00
chip_sw_example_concurrency 154.730s 2897.281us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 155.430s 4418.776us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 414.320s 5383.950us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 3759.210s 56645.945us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4434.140s 36724.794us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 62.810s 2622.697us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4434.140s 36724.794us 1 1 100.00
chip_csr_rw 414.320s 5383.950us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 8.370s 173.950us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 343.400s 4141.781us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 343.400s 4141.781us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 343.400s 4141.781us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 372.540s 4632.324us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 372.540s 4632.324us 1 1 100.00
chip_sw_uart_tx_rx_idx1 440.480s 4353.849us 1 1 100.00
chip_sw_uart_tx_rx_idx2 383.300s 5166.868us 1 1 100.00
chip_sw_uart_tx_rx_idx3 382.010s 4303.218us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 310.020s 3640.603us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 408.370s 4846.863us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 301.520s 5102.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 221.670s 5494.134us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 221.670s 5494.134us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 168.040s 2980.895us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 278.110s 6194.121us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 206.470s 4255.833us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 214.350s 4067.283us 1 1 100.00
chip_tap_straps_testunlock0 196.510s 3718.203us 1 1 100.00
chip_tap_straps_rma 419.840s 6714.007us 1 1 100.00
chip_tap_straps_prod 266.830s 5277.791us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 827.870s 10070.653us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 399.910s 5020.388us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 399.910s 5020.388us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 633.770s 7784.082us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 759.430s 9122.468us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 399.250s 3965.175us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 629.360s 6160.391us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3962.420s 18840.806us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.910s 2609.645us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 640.710s 6583.224us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.870s 2458.929us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 624.810s 7668.044us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 173.770s 3148.483us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 389.780s 5451.346us 1 1 100.00
chip_sw_clkmgr_jitter 130.360s 2984.206us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 160.660s 3279.703us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 418.940s 7519.676us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 247.620s 5433.897us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 162.260s 3694.603us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 247.620s 5433.897us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 139.950s 2959.439us 1 1 100.00
chip_sw_aes_smoketest 197.840s 3510.981us 1 1 100.00
chip_sw_aon_timer_smoketest 152.630s 3010.624us 1 1 100.00
chip_sw_clkmgr_smoketest 166.260s 3350.942us 1 1 100.00
chip_sw_csrng_smoketest 202.800s 3428.325us 1 1 100.00
chip_sw_entropy_src_smoketest 995.860s 7902.116us 1 1 100.00
chip_sw_gpio_smoketest 179.490s 2839.440us 1 1 100.00
chip_sw_hmac_smoketest 261.230s 3743.965us 1 1 100.00
chip_sw_kmac_smoketest 205.630s 3403.649us 1 1 100.00
chip_sw_otbn_smoketest 1274.550s 9824.277us 1 1 100.00
chip_sw_pwrmgr_smoketest 319.700s 6461.703us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 329.750s 5361.032us 1 1 100.00
chip_sw_rv_plic_smoketest 155.520s 2616.861us 1 1 100.00
chip_sw_rv_timer_smoketest 167.810s 3857.191us 1 1 100.00
chip_sw_rstmgr_smoketest 126.790s 2641.227us 1 1 100.00
chip_sw_sram_ctrl_smoketest 147.700s 3300.943us 1 1 100.00
chip_sw_uart_smoketest 151.960s 2835.656us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 132.080s 3006.426us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 330.060s 5119.492us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8541.790s 63686.557us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2955.320s 15827.474us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 42.546s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 192.970s 3578.609us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 191.920s 3276.070us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7159.000s 54938.396us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7941.760s 59189.069us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 56.490s 1763.751us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 56.490s 1763.751us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4434.140s 36724.794us 1 1 100.00
chip_same_csr_outstanding 1452.140s 16898.660us 1 1 100.00
chip_csr_hw_reset 155.430s 4418.776us 1 1 100.00
chip_csr_rw 414.320s 5383.950us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4434.140s 36724.794us 1 1 100.00
chip_same_csr_outstanding 1452.140s 16898.660us 1 1 100.00
chip_csr_hw_reset 155.430s 4418.776us 1 1 100.00
chip_csr_rw 414.320s 5383.950us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 40.330s 2031.235us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.200s 48.545us 1 1 100.00
xbar_smoke_large_delays 34.510s 5402.194us 1 1 100.00
xbar_smoke_slow_rsp 32.750s 3915.171us 1 1 100.00
xbar_random_zero_delays 36.080s 406.632us 1 1 100.00
xbar_random_large_delays 292.690s 52818.889us 1 1 100.00
xbar_random_slow_rsp 90.150s 9642.732us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 8.970s 137.742us 1 1 100.00
xbar_error_and_unmapped_addr 9.610s 119.196us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 29.830s 1503.549us 1 1 100.00
xbar_error_and_unmapped_addr 9.610s 119.196us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 11.520s 230.068us 1 1 100.00
xbar_access_same_device_slow_rsp 91.380s 10992.294us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 51.350s 2307.566us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 51.440s 758.904us 1 1 100.00
xbar_stress_all_with_error 10.620s 272.606us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 169.880s 719.977us 1 1 100.00
xbar_stress_all_with_reset_error 157.070s 2728.836us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2955.320s 15827.474us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2449.550s 28057.151us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2994.860s 15022.821us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 54.233s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.040s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.016s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.494s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 28.712s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 62.287s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 11.838s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 15.968s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 8.541s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9.187s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 61.187s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 75.271s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 33.433s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 87.598s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 40.012s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20.990s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 19.020s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.080s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 19.090s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 25.410s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.430s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 21.770s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.170s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.230s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.260s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 22.390s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 21.260s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.170s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 23.860s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.480s 10.320us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 153.636s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 76.236s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 66.905s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 103.167s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 86.218s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 3196.980s 17329.752us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 5980.380s 29622.817us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5991.480s 28651.333us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3466.940s 21196.983us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3091.890s 35195.198us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3091.890s 35195.198us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 165.180s 2925.850us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.910s 2609.645us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 174.360s 3203.664us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 194.630s 3194.882us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1057.540s 8652.359us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 179.050s 3453.041us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 342.340s 5237.601us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 531.750s 5697.295us 1 1 100.00
chip_plic_all_irqs_10 285.890s 4088.012us 1 1 100.00
chip_plic_all_irqs_20 407.820s 4538.498us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 182.190s 3306.436us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1245.370s 13359.099us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 192.040s 4003.612us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 156.450s 2757.504us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.164s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1070.720s 8594.938us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1064.030s 8857.480us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 761.000s 7934.366us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8143.470s 255301.375us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 261.240s 4131.622us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 319.700s 6461.703us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 261.240s 4131.622us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 435.890s 7617.175us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 435.890s 7617.175us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 299.430s 7471.844us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 420.600s 5362.972us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 608.180s 6339.734us 1 1 100.00
chip_sw_aes_idle 194.630s 3194.882us 1 1 100.00
chip_sw_hmac_enc_idle 171.690s 3055.985us 1 1 100.00
chip_sw_kmac_idle 136.200s 2790.382us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 355.150s 5566.925us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 215.060s 3854.255us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 322.170s 5838.755us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 342.130s 4269.069us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1007.590s 13852.263us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 442.340s 4550.435us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.710s 4667.549us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.290s 3780.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 428.380s 5000.235us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 361.700s 4452.519us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.800s 5072.065us 1 1 100.00
chip_sw_ast_clk_outputs 633.770s 7784.082us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 590.710s 11904.310us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.290s 3780.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 428.380s 5000.235us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 399.250s 3965.175us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 629.360s 6160.391us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3962.420s 18840.806us 1 1 100.00
chip_sw_aes_enc_jitter_en 154.910s 2609.645us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 640.710s 6583.224us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.870s 2458.929us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 624.810s 7668.044us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 173.770s 3148.483us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 389.780s 5451.346us 1 1 100.00
chip_sw_clkmgr_jitter 130.360s 2984.206us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 136.470s 2799.156us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 357.660s 4816.863us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 655.150s 7341.478us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4024.780s 24727.131us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 192.110s 3555.361us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 185.430s 3294.090us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1130.390s 11360.338us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 177.170s 2846.058us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 349.350s 4617.907us 1 1 100.00
chip_sw_flash_init_reduced_freq 1337.440s 25025.808us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11767.100s 136306.494us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 633.770s 7784.082us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 412.300s 4815.030us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 276.930s 3141.479us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1070.720s 8594.938us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2295.400s 23881.314us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 173.810s 3318.377us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 440.480s 7571.087us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 179.310s 3097.019us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2076.840s 12458.735us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 127.990s 2345.634us 1 1 100.00
chip_sw_edn_entropy_reqs 595.940s 6842.349us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 127.990s 2345.634us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2295.400s 23881.314us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 150.190s 3107.628us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1097.540s 17211.570us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 561.500s 5654.854us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 629.360s 6160.391us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 405.350s 3480.465us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 399.250s 3965.175us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3400.730s 43653.983us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1097.540s 17211.570us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 217.810s 3817.081us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3400.730s 43653.983us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 95.120s 3040.342us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 568.990s 5303.051us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 384.100s 4998.474us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 384.100s 4998.474us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 151.140s 2949.060us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.870s 2458.929us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 171.690s 3055.985us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1658.720s 12018.591us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1582.790s 12026.900us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 456.020s 5272.860us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 417.210s 5402.459us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 431.080s 4790.436us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 325.790s 3913.544us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 624.810s 7668.044us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1771.950s 13088.058us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1057.540s 8652.359us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 5337.640s 20018.637us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 156.580s 3316.220us 1 1 100.00
chip_sw_kmac_mode_kmac 211.460s 3235.427us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 173.770s 3148.483us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 139.380s 2657.598us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 726.980s 6338.716us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 136.200s 2790.382us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 342.340s 5237.601us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 214.350s 4067.283us 1 1 100.00
chip_tap_straps_rma 419.840s 6714.007us 1 1 100.00
chip_tap_straps_prod 266.830s 5277.791us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 158.810s 3060.480us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1209.090s 9341.596us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 188.570s 3394.521us 0 1 0.00
chip_sw_flash_rma_unlocked 3400.730s 43653.983us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 252.490s 3712.982us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 492.430s 6204.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 492.460s 7025.253us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 455.440s 6537.598us 0 1 0.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 291.050s 9799.070us 1 1 100.00
chip_sw_sram_ctrl_execution_main 484.240s 6778.667us 1 1 100.00
chip_prim_tl_access 95.120s 3040.342us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 590.710s 11904.310us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 442.340s 4550.435us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.710s 4667.549us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.290s 3780.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 428.380s 5000.235us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 361.700s 4452.519us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.800s 5072.065us 1 1 100.00
chip_tap_straps_dev 214.350s 4067.283us 1 1 100.00
chip_tap_straps_rma 419.840s 6714.007us 1 1 100.00
chip_tap_straps_prod 266.830s 5277.791us 1 1 100.00
chip_rv_dm_lc_disabled 170.430s 7540.215us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 140.520s 2705.273us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 109.360s 3963.789us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 88.730s 2948.394us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 105.680s 3288.574us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1695.160s 33025.619us 1 1 100.00
chip_rv_dm_lc_disabled 170.430s 7540.215us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 645.920s 11058.578us 0 1 0.00
chip_sw_lc_walkthrough_prod 804.200s 9166.512us 0 1 0.00
chip_sw_lc_walkthrough_prodend 561.600s 8811.703us 1 1 100.00
chip_sw_lc_walkthrough_rma 379.080s 6836.494us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1695.160s 33025.619us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 86.630s 2745.546us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 69.910s 2590.951us 1 1 100.00
rom_volatile_raw_unlock 105.967s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3854.100s 17202.504us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3962.420s 18840.806us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 608.180s 6339.734us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 608.180s 6339.734us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 608.180s 6339.734us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 299.640s 3812.488us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1097.540s 17211.570us 1 1 100.00
chip_sw_otbn_mem_scramble 299.640s 3812.488us 1 1 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 384.180s 5123.996us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.410s 2792.187us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1097.540s 17211.570us 1 1 100.00
chip_sw_otbn_mem_scramble 299.640s 3812.488us 1 1 100.00
chip_sw_keymgr_key_derivation 1587.010s 11549.224us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 384.180s 5123.996us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.410s 2792.187us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 309.630s 5996.516us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 158.810s 3060.480us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 252.490s 3712.982us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 492.430s 6204.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 492.460s 7025.253us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 455.440s 6537.598us 0 1 0.00
chip_sw_lc_ctrl_transition 550.070s 11179.641us 1 1 100.00
chip_prim_tl_access 95.120s 3040.342us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 95.120s 3040.342us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 778.760s 7188.119us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 182.640s 6722.202us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1164.830s 26283.945us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 251.940s 7472.856us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 341.880s 7922.239us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 333.810s 7446.904us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 861.140s 21249.445us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1103.710s 15816.365us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 435.890s 7617.175us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 986.440s 12311.598us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 329.980s 5623.211us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 182.640s 6722.202us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 278.220s 5381.860us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 311.730s 6333.521us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 273.110s 7654.637us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 152.700s 3245.616us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 741.980s 13388.411us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 592.230s 6215.854us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 901.560s 13034.061us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1828.080s 30127.119us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 152.940s 3319.591us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 291.050s 9799.070us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 291.050s 9799.070us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 901.560s 13034.061us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 741.980s 13388.411us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 329.980s 5623.211us 1 1 100.00
chip_sw_pwrmgr_smoketest 319.700s 6461.703us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 287.330s 4910.634us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 488.310s 6560.445us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 253.320s 4264.074us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1245.370s 13359.099us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 153.780s 3209.280us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1064.030s 8857.480us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 484.570s 5379.833us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 483.730s 4442.583us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 188.270s 3594.634us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 162.410s 2792.187us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 488.310s 6560.445us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 488.310s 6560.445us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 156.660s 2938.555us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1093.240s 16841.464us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 948.430s 14060.108us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 287.330s 4910.634us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 206.410s 3645.585us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 296.720s 6592.913us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 419.840s 6714.007us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 170.430s 7540.215us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 531.750s 5697.295us 1 1 100.00
chip_plic_all_irqs_10 285.890s 4088.012us 1 1 100.00
chip_plic_all_irqs_20 407.820s 4538.498us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 165.800s 2885.423us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 211.650s 3517.518us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2955.320s 15827.474us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 318.930s 5848.507us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 250.280s 4140.633us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 187.790s 2994.276us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 160.980s 2812.147us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 384.180s 5123.996us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 389.780s 5451.346us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 490.530s 8504.966us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 473.530s 8252.707us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 484.240s 6778.667us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
chip_sw_data_integrity_escalation 399.910s 5020.388us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 592.230s 6215.854us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1095.570s 24156.500us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 161.270s 3111.657us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 224.220s 3567.966us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 356.850s 4968.448us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1095.570s 24156.500us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1095.570s 24156.500us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2393.590s 21130.256us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2393.590s 21130.256us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 332.460s 6403.831us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3091.890s 35195.198us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 167.000s 3005.264us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 151.510s 2354.769us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 336.220s 4470.232us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 373.910s 4349.880us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 910.610s 8470.931us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5383.150s 31936.811us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1977.130s 11828.031us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 194.770s 3715.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 208.970s 3186.820us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 84.940s 1871.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9673.760s 71272.470us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1106.660s 7002.763us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 205.950s 4297.684us 0 1 0.00
rom_e2e_jtag_debug_dev 485.880s 7379.519us 0 1 0.00
rom_e2e_jtag_debug_rma 222.540s 4273.494us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 268.080s 5517.995us 1 1 100.00
rom_e2e_jtag_inject_dev 70.340s 2649.512us 0 1 0.00
rom_e2e_jtag_inject_rma 111.350s 3369.134us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 116.882s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 286.850s 4068.318us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 321.490s 3123.565us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1164.340s 7589.847us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1230.280s 8876.767us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 264.460s 2904.145us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 673.130s 5821.982us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 72.630s 2585.080us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 194.190s 3081.372us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 320.890s 6130.391us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 344.170s 4596.432us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 901.560s 13034.061us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 205.950s 4297.684us 0 1 0.00
rom_e2e_jtag_debug_dev 485.880s 7379.519us 0 1 0.00
rom_e2e_jtag_debug_rma 222.540s 4273.494us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 347.320s 4890.393us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 399.210s 6189.156us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5579.430s 38567.910us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5579.430s 38567.910us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 153.250s 3153.378us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 372.540s 4632.324us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3219.780s 19060.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 205.140s 3891.688us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.870s 10.360us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.160s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 159.750s 2633.763us 1 1 100.00
chip_sw_otp_ctrl_descrambling 166.310s 2587.643us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 233.630s 3872.181us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.428s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 175.300s 3305.867us 1 1 100.00
ate_bootstrap_flash_erase 685.470s 10010.240us 0 1 0.00
ate_bootstrap_one_frame 6366.850s 45514.299us 1 1 100.00
ate_bootstrap_disjoint 9971.890s 84586.075us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 41116977078058207552683902961728204023441095154077751495242134519935913472941 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 114839889448209903948589499615136435619625684399532212966794294267964697830965 None
Another command (pid=382561) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=394061) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=416040) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 90259706929892027637566649489806762927278049718861373698774453987525104045090 None
---- STDERR ----
Another command (pid=623729) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 70689986189879454899877302959989099657865304643366881756866880035291345832493 None
Another command (pid=627186) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=581561) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=585271) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 795749165362976165708464882481730276326844427431446364880160006822881935691 None
Another command (pid=483177) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=638000) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=633214) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 107404203919275573825707548592135175077204661828864915346897093390860696899084 None
Another command (pid=658911) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=686064) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=694912) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 8842251536433576277714198123427750685725155504486648448638639169898246686110 None
Another command (pid=416040) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=402041) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=445061) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 42484477139364614556420808200110438986727114442194473570916623899075159617849 None
Another command (pid=585709) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=430645) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=586788) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 52856237635159010714739614227557279835455592060753823824882379634416738106184 None
Another command (pid=581561) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=612017) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=621065) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 95114558787998515249439735817716032581681581241018592175717011015355791259180 None
---- STDERR ----
Another command (pid=610531) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=566547) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 95996690433379733970949595234130945879895207337078434349140798205923865276140 None
---- STDERR ----
Another command (pid=614752) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 99225090102499773516686530076192376726016494951777553749524230315399823027231 None
---- STDERR ----
Another command (pid=463147) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 21563620382463660453345595375788827160796745858708434839824662479543926251628 None
Another command (pid=631792) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=655356) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=491371) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 58149085220730563816743477260549722314443344279201643150475378479141234620768 None
Another command (pid=619170) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=627186) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=581561) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 73534983473981927110273747970649722914622771251342600816276214409683201017880 None
Another command (pid=763090) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=740681) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=763492) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 4549038255877650989925250696263044378406943885816572490214569428559994112473 None
Another command (pid=569341) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=639080) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=465347) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 105212545480799599516202604028423870547193163396769279594994908057806883972367 None
Another command (pid=603846) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=464896) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=578863) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 88250961459547368368911322643656815404995031761504834344473033265712921259732 None
Another command (pid=564496) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=563459) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=570234) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 57995276129982335923568071755331532173527184006233178048533108259456310103986 None
Another command (pid=463798) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=406490) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=565149) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 8919816726248221458172857341767331795104010350701076171346309436679737684617 None
Another command (pid=646225) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=631792) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=655356) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 38340591066488425064960566949623519689302774939597418859660791535428868028848 None
Another command (pid=619170) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=627186) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=581561) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 72159717488957043551360234063332810169557140895420220371785682835608247199307 None
Another command (pid=445061) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=467448) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=470088) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 18085420878628488741371039489338185121570565712543302962435545438366255598296 None
Another command (pid=409535) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=382561) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=394061) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 26418543893689730948341766066590002265435608750988007716152591033599369521268 None
Another command (pid=467448) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=470088) is running. Waiting for it to complete on the server (server_pid=273406)...
Another command (pid=463798) is running. Waiting for it to complete on the server (server_pid=273406)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 32183171608591558269941151336980871251743651746128771973001655299584110905414 367
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 80713918209941598848560383575246356942021548226100908913207452501692079352203 365
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 114282396116006742868743821436798624625848633348799867065116993594157189384286 366
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 14853138701603813874311996301600016326964224478615940312399994244221654356672 328
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 87495904558044106573613741055187513557203377665396754174053889025241683367775 328
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 23559031163237855891164871853757925261718354854389267953933498037139116780954 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 6262566375534850615656417526750577591056470168698612243738147427724744248646 344
UVM_ERROR @ 13388.411000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13388.411000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 27937265813131379528227648152892348455549540245832216649340002829320595212397 325
UVM_ERROR @ 7922.239500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7922.239500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 33064606622936841605111323897029874110214809629690416675794780291034582686444 316
UVM_ERROR @ 6333.521000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6333.521000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 115339905238627288993732799249938819302884569296541481877588815893855908710388 334
UVM_ERROR @ 24156.500000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24156.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 13162153159614035760877008899407914107294472829949029429671768646685707916530 319
UVM_ERROR @ 7617.175000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7617.175000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 5 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 46067048408615656096036070708515193056000843391284018162704844004817951331694 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 75157464604309409041813776040269880379868705144604198841429512825717836158065 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 41895429976260085096565367948521919004869791841963575121058386162134083441070 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 13802377102886122846574698826631556009249988096652434973966596203571400620973 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 65947191323106746017663932994411990652493923982791999285365137624717951119627 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 22166614005203440457102795701784930356556593866358104097964316774418701464282 369
UVM_INFO @ 11058.577820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 99042455187814290713478332301389878123490410378197295736262605563483157864818 369
UVM_INFO @ 9166.512232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 60199523100843905299629425436683499268380013785824135578616939021150732552061 341
UVM_INFO @ 6836.493846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_oneshot 111958231650167765316580270995103755044157200066813190665516789479888747598111 310
UVM_INFO @ 12018.591334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 43378163516267470427871443904142591477884504773116821388103591274064388655910 310
UVM_INFO @ 12026.900223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 83369434855524086841714973940634264139447744031061312276680879704607843309751 338
UVM_INFO @ 20018.636691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 30323505047225689856719797349198866064253806905912933226887560798679344569414 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 82641200654486303438439151674844533379528794134184614188355037271340305359336 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 55447340961634207978490918950680477221924848005634122809941601256029446844495 325
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 64975178166409874127968626766407814068270114963396694457258688510045501230861 316
UVM_ERROR @ 3081.372224 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3081.372224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 74677038537021877162536798844988184977028533215324516439705098070303945118951 312
UVM_ERROR @ 3318.377096 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3318.377096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 17212244957841355565602526502838025980494404153314552776361794602982032886806 217
TL item was: req: (cip_tl_seq_item@32190) { a_addr: 'h106e8 a_data: 'h625098d2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18ac3 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1763.751080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 19178815743373657054278339029341001138120768699813164507679460041192249534019 224
TL item was: req: (cip_tl_seq_item@31338) { a_addr: 'h105c8 a_data: 'h8cc25da8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h19e25 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2622.696965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 94956414680772598295953421461451652623928367225067158095975337980562596164404 365
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 27955025001281164990395133278769574937484837778843787239864768833687996983164 325
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 41336219271141915391299500302038658937148308807848227029519476533519392104564 367
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 86193938415809618766208700766058973383939811267553334737881190884936748119701 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 82774309925851531237305252269664902573675716918749298903438985634560186496713 301
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] 1 test run
chip_sw_sleep_pin_mio_dio_val 48758141902866769137868324581194372211163714506027706848545857196131125924148 451
UVM_INFO @ 2980.895000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 104253936002044756161715223208304500736117371969914583104573740385308365893837 327
UVM_INFO @ 4140.633450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 52238782564766515492565820152090984308461604132312666606396875301276211834373 309
UVM_INFO @ 3394.520641 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 90201375191401015195015954914053628231278817852284980841803246296716721244339 342
UVM_INFO @ 6537.597720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 54219559260711817199761603490904908369914071750737682753143487991794307024729 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 86602099775377080115829005851894495205006609477099906028122616091505669562829 318
UVM_ERROR @ 6722.201528 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6722.201528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 90446437844547726380003005989536801090893653293833622231200910297140978016132 313
UVM_ERROR @ 3245.615700 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3245.615700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 78042078597933706643706361335622269286747571732497400358864984807595450716272 332
UVM_INFO @ 35195.198471 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:377)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 13571739518154775560192660550195073339643765490638178616964688206159305542886 307
UVM_INFO @ 3453.041336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 2983620930311595184001852210458724840059680980382871559284459963149199747621 308
UVM_INFO @ 2757.503735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 74154050104115636781088898772007401476274508432783307566826165227772241287393 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 14992972618916338518972934215333847802651347525645452443159299898716051059687 343
UVM_INFO @ 4068.317636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 79597387967863269492602205042274288021215130092638582171453486097005045246455 246
UVM_INFO @ 7540.214850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 11685413529575616326084223810645843221990004338794004226975419891214542256478 312
UVM_INFO @ 3578.609000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 96994575231716268626915574860708593608485127556456499921240539938633405581021 318
UVM_INFO @ 3276.070000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 84365733355142455186297655745584086382068371541923531880227751907369389009301 327
UVM_INFO @ 9122.467778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 42173280096379626108170172406891458700478518966758194585718962264399615686277 272
UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 956771678349443590226431618256331145011202676219314719854034763241847505995 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 101068847231589027459717419128689168345465634456251182941584338238459094123383 325
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) 1 test run
rom_e2e_jtag_debug_test_unlocked0 2991575912281062911137559843743836888899323044475568603217716287525140356403 317
UVM_INFO @ 4297.683607 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 102348714184028372567335456594879523820216386573988447394060854952929481829064 319
UVM_INFO @ 17329.752226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 62213935411697248106232779486807165288082128930304811813755939619970191968045 327
UVM_ERROR @ 5119.492170 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5119.492170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---