Simulation Results: clkmgr

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.95 %
  • code
  • 97.73 %
  • assert
  • 94.07 %
  • func
  • 84.05 %
  • line
  • 98.88 %
  • branch
  • 98.64 %
  • cond
  • 91.95 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.940s 40.821us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.740s 17.491us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.390s 326.738us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.030s 391.655us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.070s 64.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
clkmgr_csr_aliasing 2.030s 391.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.780s 27.164us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.970s 54.940us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.840s 47.260us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.840s 54.617us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.940s 40.821us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.310s 240.765us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.370s 1455.071us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.310s 240.765us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 11.260s 2595.971us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.690s 21.008us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.810s 83.156us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.810s 83.156us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 17.491us 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
clkmgr_csr_aliasing 2.030s 391.655us 1 1 100.00
clkmgr_same_csr_outstanding 0.920s 60.053us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 17.491us 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
clkmgr_csr_aliasing 2.030s 391.655us 1 1 100.00
clkmgr_same_csr_outstanding 0.920s 60.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.070s 36.623us 0 1 0.00
clkmgr_tl_intg_err 1.410s 84.578us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 104.712us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 104.712us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 104.712us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 104.712us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 11.380s 2059.858us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.410s 84.578us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.310s 240.765us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.370s 1455.071us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.510s 104.712us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.940s 25.879us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.740s 22.686us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 15.667us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 0 1 0.00
clkmgr_clk_handshake_intersig_mubi 0.660s 26.085us 0 1 0.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.690s 15.998us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.070s 36.623us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 46.173us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.070s 36.623us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.140s 141.111us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 25.100s 6105.175us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 8173928169501268042734278655958587077843798964591233049436132905804769537491 74
UVM_INFO @ 26084518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 36439967878482199116575209629884712421005790245632012883267766460085466109657 75
UVM_INFO @ 2059858241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 69694723116452544201124955583482153615196917887963969149105756359093154852844 82
UVM_INFO @ 36622676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---