Simulation Results: csrng

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.32 %
  • code
  • 92.27 %
  • assert
  • 94.54 %
  • func
  • 75.15 %
  • block
  • 96.92 %
  • line
  • 97.69 %
  • branch
  • 92.43 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 84.317us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 14.305us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 103.726us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 322.657us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 275.584us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 21.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 103.726us 1 1 100.00
csrng_csr_aliasing 5.000s 275.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 118.811us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 102.000s 9295.047us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 102.000s 9295.047us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 121.000s 5237.967us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 57.736us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 16.006us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 87.389us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 87.389us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 14.305us 1 1 100.00
csrng_csr_rw 3.000s 103.726us 1 1 100.00
csrng_csr_aliasing 5.000s 275.584us 1 1 100.00
csrng_same_csr_outstanding 5.000s 200.017us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 14.305us 1 1 100.00
csrng_csr_rw 3.000s 103.726us 1 1 100.00
csrng_csr_aliasing 5.000s 275.584us 1 1 100.00
csrng_same_csr_outstanding 5.000s 200.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
csrng_tl_intg_err 5.000s 294.210us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 9.704us 0 1 0.00
csrng_csr_rw 3.000s 103.726us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 118.811us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 121.000s 5237.967us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 118.811us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 121.000s 5237.967us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 118.811us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 294.210us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
csrng_sec_cm 3.000s 71.147us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 58.796us 1 1 100.00
csrng_err 3.000s 24.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.105s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 34092142644127728268398475342359702897480550837756205112238614182263549049004 99
UVM_INFO @ 9704154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 67939945579521209307832035326583931376811024846334905908452715032306167500658 None