Simulation Results: edn/edn0

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.34 %
  • code
  • 78.22 %
  • assert
  • 95.44 %
  • func
  • 79.37 %
  • line
  • 96.96 %
  • branch
  • 88.98 %
  • cond
  • 83.75 %
  • toggle
  • 73.00 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 29.515us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 76.488us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 26.729us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.170s 641.121us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.090s 83.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.680s 32.007us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 26.729us 1 1 100.00
edn_csr_aliasing 1.090s 83.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 53.402us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 53.402us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 53.402us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.020s 23.545us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.420s 63.357us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 47.763us 1 1 100.00
disable 2 2 100.00
edn_disable 0.870s 13.927us 1 1 100.00
edn_disable_auto_req_mode 0.960s 76.220us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.490s 1403.500us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 14.047us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 15.270us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.580s 149.532us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.580s 149.532us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 76.488us 1 1 100.00
edn_csr_rw 0.810s 26.729us 1 1 100.00
edn_csr_aliasing 1.090s 83.330us 1 1 100.00
edn_same_csr_outstanding 1.320s 199.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 76.488us 1 1 100.00
edn_csr_rw 0.810s 26.729us 1 1 100.00
edn_csr_aliasing 1.090s 83.330us 1 1 100.00
edn_same_csr_outstanding 1.320s 199.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
edn_tl_intg_err 1.530s 260.501us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 29.371us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.420s 63.357us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.420s 63.357us 1 1 100.00
edn_sec_cm 4.460s 458.085us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.420s 63.357us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.530s 260.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 53.760s 6827.816us 1 1 100.00