Simulation Results: edn/edn1

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.63 %
  • code
  • 83.72 %
  • assert
  • 98.44 %
  • func
  • 77.73 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 89.31 %
  • toggle
  • 94.99 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 20.368us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 21.634us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.710s 42.262us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.460s 111.808us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.960s 26.715us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 166.704us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.710s 42.262us 1 1 100.00
edn_csr_aliasing 0.960s 26.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.880s 153.150us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.880s 153.150us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.880s 153.150us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 23.288us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 51.246us 1 1 100.00
errs 1 1 100.00
edn_err 0.760s 35.046us 1 1 100.00
disable 2 2 100.00
edn_disable 0.720s 127.614us 1 1 100.00
edn_disable_auto_req_mode 0.930s 26.982us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.430s 130.695us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 28.693us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.730s 55.620us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.430s 313.175us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.430s 313.175us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 21.634us 1 1 100.00
edn_csr_rw 0.710s 42.262us 1 1 100.00
edn_csr_aliasing 0.960s 26.715us 1 1 100.00
edn_same_csr_outstanding 1.010s 62.940us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 21.634us 1 1 100.00
edn_csr_rw 0.710s 42.262us 1 1 100.00
edn_csr_aliasing 0.960s 26.715us 1 1 100.00
edn_same_csr_outstanding 1.010s 62.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
edn_tl_intg_err 1.820s 377.241us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 18.984us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 51.246us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 51.246us 1 1 100.00
edn_sec_cm 2.350s 403.001us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 51.246us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.820s 377.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 9.260s 480.101us 1 1 100.00