Simulation Results: flash_ctrl

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 93.70 %
  • assert
  • 96.94 %
  • func
  • 96.01 %
  • line
  • 96.04 %
  • branch
  • 97.14 %
  • cond
  • 93.61 %
  • toggle
  • 96.66 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
96.55%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 34.350s 84.800us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.690s 44.359us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.210s 117.937us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 43.410s 947.939us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.900s 2912.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.590s 144.059us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
flash_ctrl_csr_aliasing 22.900s 2912.922us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.910s 31.138us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.590s 63.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.510s 28.591us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 42.690s 121.744us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1188.300s 97667.885us 1 1 100.00
flash_ctrl_hw_rma_reset 561.150s 160188.665us 1 1 100.00
flash_ctrl_lcmgr_intg 5.880s 43.208us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1143.550s 300814.603us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 195.070s 2714.076us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.340s 69.729us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2306.050s 54187.567us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 39.420s 221.913us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 14.950s 34.170us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.070s 85.956us 0 1 0.00
flash_ctrl_re_evict 16.370s 137.661us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 90.810s 2874.783us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 90.810s 2874.783us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 522.740s 148576.349us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.310s 1532.719us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 221.060s 123.053us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 357.480s 7441.190us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 338.600s 390.381us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 958.910s 979.752us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.270s 95.314us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 128.210s 1727.296us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.460s 59.545us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.870s 18.139us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 186.360s 432.018us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 68.900s 23345.255us 1 1 100.00
flash_ctrl_otp_reset 60.550s 478.962us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1188.300s 97667.885us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 97.250s 3870.863us 1 1 100.00
flash_ctrl_intr_wr 53.820s 5000.593us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 100.320s 28220.169us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 146.340s 93858.044us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 58.910s 8272.064us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 38.050s 1419.199us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 15.070s 56.746us 1 1 100.00
flash_ctrl_ro_derr 92.860s 1497.146us 1 1 100.00
flash_ctrl_rw_derr 141.390s 3993.035us 1 1 100.00
flash_ctrl_derr_detect 97.960s 992.252us 1 1 100.00
flash_ctrl_integrity 428.840s 8400.506us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.600s 105.776us 1 1 100.00
flash_ctrl_ro_serr 95.570s 784.674us 1 1 100.00
flash_ctrl_rw_serr 112.870s 1388.509us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 74.820s 5567.445us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 63.820s 1254.190us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 108.510s 10654.364us 1 1 100.00
flash_ctrl_write_word_sweep 9.670s 90.908us 1 1 100.00
flash_ctrl_read_word_sweep 6.930s 128.790us 1 1 100.00
flash_ctrl_ro 82.780s 2925.069us 1 1 100.00
flash_ctrl_rw 135.470s 1937.380us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.490s 559.621us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 554.350s 39837.712us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 38.180s 10034.468us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.770s 24.558us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.680s 33.596us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 14.620s 107.292us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 14.620s 107.292us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.210s 117.937us 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
flash_ctrl_csr_aliasing 22.900s 2912.922us 1 1 100.00
flash_ctrl_same_csr_outstanding 12.320s 79.661us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.210s 117.937us 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
flash_ctrl_csr_aliasing 22.900s 2912.922us 1 1 100.00
flash_ctrl_same_csr_outstanding 12.320s 79.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 43.490s 449.940us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
flash_ctrl_tl_intg_err 400.810s 1369.325us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 400.810s 1369.325us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 400.810s 1369.325us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.910s 259.892us 1 1 100.00
flash_ctrl_wr_intg 7.110s 193.098us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 34.350s 84.800us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 60.550s 478.962us 1 1 100.00
flash_ctrl_disable 9.460s 59.545us 1 1 100.00
flash_ctrl_sec_info_access 45.730s 926.151us 1 1 100.00
flash_ctrl_connect 8.870s 18.139us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.910s 363.760us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.550s 30.226us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 59.830s 107.173us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.460s 59.545us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.910s 259.892us 1 1 100.00
flash_ctrl_access_after_disable 5.940s 40.462us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.350s 37.519us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.460s 59.545us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.310s 1532.719us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 135.470s 1937.380us 0 1 0.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 112.870s 1388.509us 1 1 100.00
flash_ctrl_rw_derr 141.390s 3993.035us 1 1 100.00
flash_ctrl_integrity 428.840s 8400.506us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1188.300s 97667.885us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 18.660s 923.040us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 11.540s 78.407us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.950s 24.133us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1721.900s 3241.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.910s 369.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 28.760s 46.615us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 1 test run
flash_ctrl_rw 11545123816943747463725203246342258682193332876212929545777720434717731660435 108
UVM_INFO @ 1937380.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_rw_evict_all_en 16556399405253073013926586813834388769983866114507862033245967097072443156282 108
UVM_INFO @ 85956.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---