Simulation Results: hmac

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.76 %
  • code
  • 97.74 %
  • assert
  • 96.29 %
  • func
  • 42.24 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.960s 176.886us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.720s 25.092us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.690s 54.351us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.520s 4529.694us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.470s 1568.435us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.750s 152.929us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.690s 54.351us 1 1 100.00
hmac_csr_aliasing 4.470s 1568.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 22.540s 8964.325us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 82.830s 11206.630us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.980s 224.870us 1 1 100.00
hmac_test_sha384_vectors 20.740s 330.371us 1 1 100.00
hmac_test_sha512_vectors 342.430s 15871.763us 1 1 100.00
hmac_test_hmac256_vectors 7.490s 1941.846us 1 1 100.00
hmac_test_hmac384_vectors 7.460s 582.379us 1 1 100.00
hmac_test_hmac512_vectors 8.050s 4504.149us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.020s 7350.269us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 200.620s 2339.402us 1 1 100.00
error 1 1 100.00
hmac_error 41.930s 1274.068us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 32.890s 4216.120us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.960s 176.886us 1 1 100.00
hmac_long_msg 22.540s 8964.325us 1 1 100.00
hmac_back_pressure 82.830s 11206.630us 1 1 100.00
hmac_datapath_stress 200.620s 2339.402us 1 1 100.00
hmac_burst_wr 16.020s 7350.269us 1 1 100.00
hmac_stress_all 183.720s 96910.099us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.960s 176.886us 1 1 100.00
hmac_long_msg 22.540s 8964.325us 1 1 100.00
hmac_back_pressure 82.830s 11206.630us 1 1 100.00
hmac_datapath_stress 200.620s 2339.402us 1 1 100.00
hmac_wipe_secret 32.890s 4216.120us 1 1 100.00
hmac_test_sha256_vectors 8.980s 224.870us 1 1 100.00
hmac_test_sha384_vectors 20.740s 330.371us 1 1 100.00
hmac_test_sha512_vectors 342.430s 15871.763us 1 1 100.00
hmac_test_hmac256_vectors 7.490s 1941.846us 1 1 100.00
hmac_test_hmac384_vectors 7.460s 582.379us 1 1 100.00
hmac_test_hmac512_vectors 8.050s 4504.149us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.960s 176.886us 1 1 100.00
hmac_long_msg 22.540s 8964.325us 1 1 100.00
hmac_back_pressure 82.830s 11206.630us 1 1 100.00
hmac_datapath_stress 200.620s 2339.402us 1 1 100.00
hmac_burst_wr 16.020s 7350.269us 1 1 100.00
hmac_error 41.930s 1274.068us 1 1 100.00
hmac_wipe_secret 32.890s 4216.120us 1 1 100.00
hmac_test_sha256_vectors 8.980s 224.870us 1 1 100.00
hmac_test_sha384_vectors 20.740s 330.371us 1 1 100.00
hmac_test_sha512_vectors 342.430s 15871.763us 1 1 100.00
hmac_test_hmac256_vectors 7.490s 1941.846us 1 1 100.00
hmac_test_hmac384_vectors 7.460s 582.379us 1 1 100.00
hmac_test_hmac512_vectors 8.050s 4504.149us 1 1 100.00
hmac_stress_all 183.720s 96910.099us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 183.720s 96910.099us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.610s 45.463us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 24.696us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.220s 1517.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.220s 1517.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.720s 25.092us 1 1 100.00
hmac_csr_rw 0.690s 54.351us 1 1 100.00
hmac_csr_aliasing 4.470s 1568.435us 1 1 100.00
hmac_same_csr_outstanding 1.410s 88.866us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.720s 25.092us 1 1 100.00
hmac_csr_rw 0.690s 54.351us 1 1 100.00
hmac_csr_aliasing 4.470s 1568.435us 1 1 100.00
hmac_same_csr_outstanding 1.410s 88.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 338.194us 1 1 100.00
hmac_tl_intg_err 1.760s 389.745us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.760s 389.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.960s 176.886us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.490s 115.959us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 64.170s 4454.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.240s 210.172us 1 1 100.00