Simulation Results: i2c

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.85 %
  • code
  • 81.17 %
  • assert
  • 97.25 %
  • func
  • 82.14 %
  • line
  • 96.35 %
  • branch
  • 92.19 %
  • cond
  • 84.78 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 13.240s 5735.490us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 4.960s 2162.279us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.830s 26.423us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.970s 18.906us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.630s 304.457us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.700s 1543.321us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.090s 23.426us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.970s 18.906us 1 1 100.00
i2c_csr_aliasing 1.700s 1543.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.130s 99.565us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 665.710s 87530.869us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 496.210s 72471.111us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.740s 48.116us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 83.250s 5767.660us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 23.460s 5974.838us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.290s 954.072us 1 1 100.00
i2c_host_fifo_fmt_empty 5.140s 401.850us 1 1 100.00
i2c_host_fifo_reset_rx 4.410s 581.590us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 27.840s 7540.430us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.240s 2967.887us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.990s 175.772us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.020s 2263.969us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 36.630s 9282.573us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.140s 390.578us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 18.230s 1191.826us 1 1 100.00
i2c_target_intr_smoke 3.660s 7882.984us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.000s 494.210us 1 1 100.00
i2c_target_fifo_reset_tx 1.260s 797.556us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 107.300s 62701.559us 1 1 100.00
i2c_target_stress_rd 18.230s 1191.826us 1 1 100.00
i2c_target_intr_stress_wr 3.620s 6886.245us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.520s 5361.515us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 70.880s 2904.731us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.400s 3180.471us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 3.660s 11161.723us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.330s 434.936us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.440s 372.821us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 496.210s 72471.111us 1 1 100.00
i2c_host_perf_precise 1.460s 50.590us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.240s 2967.887us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.640s 96.067us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.070s 593.480us 1 1 100.00
i2c_target_nack_acqfull_addr 2.260s 1109.043us 1 1 100.00
i2c_target_nack_txstretch 1.480s 273.900us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 2.810s 328.121us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.450s 455.565us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.770s 43.234us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.930s 21.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.270s 170.066us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.270s 170.066us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.830s 26.423us 1 1 100.00
i2c_csr_rw 0.970s 18.906us 1 1 100.00
i2c_csr_aliasing 1.700s 1543.321us 1 1 100.00
i2c_same_csr_outstanding 1.040s 80.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.830s 26.423us 1 1 100.00
i2c_csr_rw 0.970s 18.906us 1 1 100.00
i2c_csr_aliasing 1.700s 1543.321us 1 1 100.00
i2c_same_csr_outstanding 1.040s 80.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.470s 303.860us 1 1 100.00
i2c_sec_cm 0.960s 137.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.470s 303.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.770s 537.696us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.470s 136.381us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 9.990s 990.698us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 62442144557797679386299007829703675644695820955872563632234861110666173408993 87
UVM_INFO @ 537695924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 25883933830485068042905401420419661849922007312101755486667619809752220953920 86
UVM_INFO @ 990697679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 1 test run
i2c_host_error_intr 15892046384856559327805365417610363528886186133013760462575054146010727338616 120
UVM_INFO @ 99564965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: 1 test run
i2c_host_stress_all 19670447212595784473024607505515930086267600475787051968623514787027233705194 153
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4596598
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 93780632422563966138001258337053261140241646636784115739197337028727230449011 84
UVM_INFO @ 2263968566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 73312970051835670547981979081264477005489135067873991525823544455192177069500 78
UVM_INFO @ 136380912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 22949548301231162893076226311860157431782022336486521050050872934117223312606 79
UVM_INFO @ 11161722988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 46200917457754935895120158225163354440559062779716184615281907886240732037033 87
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 95798585872839002480386031318198659765585708321258960372664769021985341556577 78
UVM_INFO @ 273899555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---