Simulation Results: lc_ctrl/volatile_unlock_disabled

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.28 %
  • code
  • 83.76 %
  • assert
  • 94.55 %
  • func
  • 92.53 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.65 %
  • toggle
  • 86.35 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.810s 180.100us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.110s 78.718us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.962us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.470s 66.141us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 244.744us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.230s 19.937us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 53.962us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 244.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.450s 461.672us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1526.910us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.120s 14.525us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.890s 120.857us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.610s 1549.917us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_prog_failure 1.890s 120.857us 1 1 100.00
lc_ctrl_errors 4.610s 1549.917us 1 1 100.00
lc_ctrl_security_escalation 5.030s 366.320us 1 1 100.00
lc_ctrl_jtag_state_failure 71.160s 34987.280us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.410s 3794.297us 1 1 100.00
lc_ctrl_jtag_errors 31.010s 6622.526us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.430s 201.102us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.280s 449.214us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.410s 3794.297us 1 1 100.00
lc_ctrl_jtag_errors 31.010s 6622.526us 1 1 100.00
lc_ctrl_jtag_access 11.670s 2472.451us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.250s 5382.067us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.420s 207.480us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.200s 40.182us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.000s 3047.346us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.320s 498.187us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.190s 28.226us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.910s 351.813us 1 1 100.00
lc_ctrl_jtag_alert_test 1.140s 98.299us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.100s 1255.141us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.810s 24.700us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.190s 4747.809us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 22.448us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.010s 288.430us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.010s 288.430us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 78.718us 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.962us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 244.744us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 56.485us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 78.718us 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.962us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 244.744us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 56.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
lc_ctrl_tl_intg_err 2.160s 161.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.160s 161.983us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 1526.910us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.470s 1159.492us 1 1 100.00
lc_ctrl_sec_cm 9.500s 3134.236us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.030s 366.320us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.450s 461.672us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.280s 449.214us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.900s 879.408us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.900s 879.408us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.760s 361.255us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.890s 1821.978us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.890s 1821.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 20.440s 1061.602us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 24889084731981455987010864994699697903240289033944234192153201531331174173753 377
UVM_INFO @ 1061601718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---