Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.52 %
  • code
  • 84.48 %
  • assert
  • 94.55 %
  • func
  • 92.53 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 79.54 %
  • toggle
  • 87.33 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.950s 110.071us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 24.458us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.910s 22.904us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.630s 215.588us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 156.672us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 65.253us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.910s 22.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 156.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 7.560s 75.042us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.320s 271.372us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.880s 36.039us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 1125.780us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.900s 1790.924us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_prog_failure 3.000s 1125.780us 1 1 100.00
lc_ctrl_errors 5.900s 1790.924us 1 1 100.00
lc_ctrl_security_escalation 5.690s 1645.768us 1 1 100.00
lc_ctrl_jtag_state_failure 22.820s 1790.562us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.480s 61.653us 1 1 100.00
lc_ctrl_jtag_errors 42.560s 2204.250us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.900s 261.120us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.500s 1171.303us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.480s 61.653us 1 1 100.00
lc_ctrl_jtag_errors 42.560s 2204.250us 1 1 100.00
lc_ctrl_jtag_access 1.640s 398.556us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.110s 637.183us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.290s 1493.860us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.660s 240.180us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 24.920s 1598.803us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.180s 359.116us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.100s 100.265us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.010s 129.545us 1 1 100.00
lc_ctrl_jtag_alert_test 0.960s 143.081us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.650s 782.830us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.100s 24.988us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 53.910s 7504.606us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.770s 33.210us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.410s 115.790us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.410s 115.790us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 24.458us 1 1 100.00
lc_ctrl_csr_rw 0.910s 22.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 156.672us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.430s 30.124us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 24.458us 1 1 100.00
lc_ctrl_csr_rw 0.910s 22.904us 1 1 100.00
lc_ctrl_csr_aliasing 1.230s 156.672us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.430s 30.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
lc_ctrl_tl_intg_err 1.330s 67.997us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.330s 67.997us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.320s 271.372us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.000s 370.367us 1 1 100.00
lc_ctrl_sec_cm 7.880s 1840.380us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.690s 1645.768us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 7.560s 75.042us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.500s 1171.303us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.450s 972.788us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.450s 972.788us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.270s 401.883us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.440s 1014.713us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.440s 1014.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 60.720s 3132.764us 1 1 100.00