Simulation Results: otbn

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.67 %
  • code
  • 94.06 %
  • assert
  • 90.35 %
  • func
  • 96.61 %
  • block
  • 99.29 %
  • line
  • 99.46 %
  • branch
  • 91.11 %
  • toggle
  • 88.09 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 73.018us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 28.000s 56.215us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 28.000s 15.771us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 30.000s 90.332us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 21.738us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 33.000s 34.558us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 28.000s 15.771us 1 1 100.00
otbn_csr_aliasing 30.000s 21.738us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 34.000s 750.492us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 23.000s 591.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 22.000s 80.535us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 46.000s 1172.425us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 49.000s 227.155us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 72.000s 256.007us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 28.000s 254.078us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 27.979us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 216.942us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 29.000s 22.102us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 17.000s 26.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 41.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 41.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 28.000s 56.215us 1 1 100.00
otbn_csr_rw 28.000s 15.771us 1 1 100.00
otbn_csr_aliasing 30.000s 21.738us 1 1 100.00
otbn_same_csr_outstanding 4.000s 16.657us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 28.000s 56.215us 1 1 100.00
otbn_csr_rw 28.000s 15.771us 1 1 100.00
otbn_csr_aliasing 30.000s 21.738us 1 1 100.00
otbn_same_csr_outstanding 4.000s 16.657us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 24.000s 29.112us 1 1 100.00
otbn_dmem_err 30.000s 77.998us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 29.000s 46.673us 0 1 0.00
otbn_controller_ispr_rdata_err 32.000s 107.328us 1 1 100.00
otbn_mac_bignum_acc_err 20.000s 57.760us 1 1 100.00
otbn_urnd_err 7.000s 48.578us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 21.000s 27.136us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 18.007us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 27.500us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
otbn_tl_intg_err 10.000s 65.395us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 4.199us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 73.018us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 30.000s 77.998us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 24.000s 29.112us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 65.395us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 254.078us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 24.000s 29.112us 1 1 100.00
otbn_dmem_err 30.000s 77.998us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.979us 0 1 0.00
otbn_illegal_mem_acc 21.000s 27.136us 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 24.000s 29.112us 1 1 100.00
otbn_dmem_err 30.000s 77.998us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.979us 0 1 0.00
otbn_illegal_mem_acc 21.000s 27.136us 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 28.000s 254.078us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 24.000s 29.112us 1 1 100.00
otbn_dmem_err 30.000s 77.998us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 27.979us 0 1 0.00
otbn_illegal_mem_acc 21.000s 27.136us 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 14.145us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 21.029us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 18.000s 115.014us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 18.000s 115.014us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 25.206us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 36.384us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 17.000s 135.539us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 17.000s 135.539us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 11.000s 354.572us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 49.000s 227.155us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 48.725us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 19.890us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 685.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 59.000s 608.119us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 27.077us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 15994087830694762501566872520851003945910933225957081885595760971741070497042 114
UVM_INFO @ 46673179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 89438051471384827683594496938027961585164683043220856551559740111947928676788 216
UVM_INFO @ 608118976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 66996339324994689245769747420999380499670376014422507651761799055928538934201 107
UVM_ERROR @ 27978758 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 27978758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 65606402660354161235972873102797343008157932104869310154848918206915394125873 86
UVM_INFO @ 4199358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---