Simulation Results: pwrmgr

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.51 %
  • code
  • 95.56 %
  • assert
  • 98.96 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.19 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.650s 26.342us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 25.721us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.400s 190.080us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.900s 19.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.910s 50.582us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 19.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.900s 128.870us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.900s 128.870us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.850s 52.198us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 46.777us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.590s 67.514us 1 1 100.00
pwrmgr_reset_invalid 1.090s 96.080us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.590s 67.514us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.910s 253.213us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 170.227us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.470s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.170s 355.087us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.750s 41.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.710s 476.827us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.710s 476.827us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 25.721us 1 1 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 19.864us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 30.775us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 25.721us 1 1 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 19.864us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 30.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.280s 482.362us 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.280s 482.362us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.520s 992.097us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.910s 253.213us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.580s 1496.650us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.720s 85.217us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 38.511us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.600s 695.105us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.820s 34.229us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 59.266us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.040s 258.121us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 52.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.790s 248.888us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.490s 5964.718us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 21288331091245304339340145837472745334145019352223055289314467352532501611855 79
UVM_ERROR @ 248888081 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 248888081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 11627284335774379923912916414975378749091515310007215110965954882490033614242 181
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---