Simulation Results: rom_ctrl/32kb

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 92.28 %
  • assert
  • 97.24 %
  • func
  • 96.66 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 95.25 %
  • toggle
  • 94.59 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.470s 605.281us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.160s 882.145us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.830s 125.219us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.860s 124.355us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 537.552us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.620s 228.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.830s 125.219us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 537.552us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.350s 385.731us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.540s 165.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.430s 84.416us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.080s 2151.868us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.550s 218.927us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.480s 992.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.600s 163.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.600s 163.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.160s 882.145us 1 1 100.00
rom_ctrl_csr_rw 3.830s 125.219us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 537.552us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.490s 123.977us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.160s 882.145us 1 1 100.00
rom_ctrl_csr_rw 3.830s 125.219us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 537.552us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.490s 123.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.300s 1095.349us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
rom_ctrl_tl_intg_err 44.490s 256.426us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.470s 605.281us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.470s 605.281us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.470s 605.281us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 44.490s 256.426us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
rom_ctrl_kmac_err_chk 6.550s 218.927us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 38.240s 3802.945us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.300s 1095.349us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 103.470s 5420.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 189.150s 2694.889us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 76266718759168858555202134906896642745359900174643661973833552529620095046895 79
UVM_INFO @ 84416051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 51772537693405940896322927406694117129811761671955941916261237137031034146688 102
UVM_INFO @ 3802945233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---