Simulation Results: rom_ctrl/64kb

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.77 %
  • code
  • 98.54 %
  • assert
  • 97.39 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.07 %
  • toggle
  • 95.54 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.480s 1099.392us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.550s 309.923us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.090s 4140.874us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.970s 542.591us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.770s 1024.001us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.260s 756.900us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.090s 4140.874us 1 1 100.00
rom_ctrl_csr_aliasing 8.770s 1024.001us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.810s 520.126us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.890s 555.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.300s 992.103us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 23.850s 1617.243us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 19.130s 9901.311us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.290s 727.453us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.080s 294.166us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.080s 294.166us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.550s 309.923us 1 1 100.00
rom_ctrl_csr_rw 7.090s 4140.874us 1 1 100.00
rom_ctrl_csr_aliasing 8.770s 1024.001us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.700s 726.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.550s 309.923us 1 1 100.00
rom_ctrl_csr_rw 7.090s 4140.874us 1 1 100.00
rom_ctrl_csr_aliasing 8.770s 1024.001us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.700s 726.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.550s 3083.028us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
rom_ctrl_tl_intg_err 102.840s 1672.712us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.480s 1099.392us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.480s 1099.392us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.480s 1099.392us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 102.840s 1672.712us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
rom_ctrl_kmac_err_chk 19.130s 9901.311us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 92.350s 2750.068us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.550s 3083.028us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 240.590s 1973.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 42.190s 19719.590us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 16129425239165480203609680459592830547245675340762879693257851206028298048965 79
UVM_INFO @ 992103034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---