Simulation Results: rstmgr

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.83 %
  • code
  • 99.20 %
  • assert
  • 98.53 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 98.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.170s 131.023us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.840s 140.527us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.720s 2490.183us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.661us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.150s 159.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.150s 243.583us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.390s 159.816us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.490s 339.536us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.420s 921.579us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.420s 921.579us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.420s 921.579us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.420s 921.579us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 29.000s 12400.206us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.730s 81.691us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.280s 124.274us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.280s 124.274us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 140.527us 1 1 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.661us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 230.417us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.840s 140.527us 1 1 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.661us 1 1 100.00
rstmgr_same_csr_outstanding 1.390s 230.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.140s 16933.370us 1 1 100.00
rstmgr_tl_intg_err 1.430s 436.405us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.140s 16933.370us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.140s 16933.370us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.430s 436.405us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.950s 182.371us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.110s 2806.086us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.120s 302.251us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.140s 16933.370us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.740s 72.362us 1 1 100.00