Simulation Results: rv_timer

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.80 %
  • code
  • 100.00 %
  • assert
  • 98.41 %
  • func
  • 95.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.100s 605.572us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.720s 46.757us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.800s 29.027us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.160s 351.732us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.740s 36.979us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.920s 41.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.800s 29.027us 1 1 100.00
rv_timer_csr_aliasing 0.740s 36.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 562.261us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.820s 1496.413us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 21.000s 47753.064us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 21.000s 47753.064us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.130s 1721.136us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 15.513us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 23.475us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.550s 210.314us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.550s 210.314us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.720s 46.757us 1 1 100.00
rv_timer_csr_rw 0.800s 29.027us 1 1 100.00
rv_timer_csr_aliasing 0.740s 36.979us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 15.165us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.720s 46.757us 1 1 100.00
rv_timer_csr_rw 0.800s 29.027us 1 1 100.00
rv_timer_csr_aliasing 0.740s 36.979us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 15.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.860s 73.318us 1 1 100.00
rv_timer_tl_intg_err 0.960s 250.686us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.960s 250.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.350s 308.203us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.710s 43.271us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 32.030s 4038.264us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 88910517268969521471225181171714603062351712454989873491851372502031755691540 75
UVM_INFO @ 308203210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 15308263675064143703140197534914980513394890004587544040187121903586788540880 78
UVM_INFO @ 562260609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 33013826391533257102314569769814587832659827705775699264338862967426324358520 75
UVM_INFO @ 43270719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---