Simulation Results: spi_host

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.81 %
  • code
  • 91.01 %
  • assert
  • 96.60 %
  • func
  • 87.82 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 72.56 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 1939.050us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 140.690us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 51.117us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 580.208us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 67.072us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 85.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 51.117us 1 1 100.00
spi_host_csr_aliasing 1.000s 67.072us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 28.574us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 40.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.195us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 1.000s 104.454us 1 1 100.00
spi_host_error_cmd 2.000s 29.760us 1 1 100.00
spi_host_event 19.000s 4951.862us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 41.743us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 41.743us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 41.743us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 92.000s 7314.467us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 49.893us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 33.410us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 41.743us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 41.743us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 1939.050us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 1939.050us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 54.801us 1 1 100.00
spien 1 1 100.00
spi_host_spien 179.000s 9020.325us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 21.000s 2034.633us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 90.402us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 1.000s 104.454us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 18.092us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 18.594us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 194.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 194.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 140.690us 1 1 100.00
spi_host_csr_rw 1.000s 51.117us 1 1 100.00
spi_host_csr_aliasing 1.000s 67.072us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 78.595us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 140.690us 1 1 100.00
spi_host_csr_rw 1.000s 51.117us 1 1 100.00
spi_host_csr_aliasing 1.000s 67.072us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 78.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 98.105us 1 1 100.00
spi_host_sec_cm 1.000s 251.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 98.105us 1 1 100.00