Simulation Results: sram_ctrl/main

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 96.73 %
  • assert
  • 98.10 %
  • func
  • 95.40 %
  • block
  • 96.03 %
  • line
  • 96.83 %
  • branch
  • 94.01 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1477.597us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.889us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.571us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 202.861us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 50.503us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1412.884us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 37.571us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 50.503us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 95.000s 2961.867us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 54.000s 12067.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 20039.634us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 222.000s 37796.616us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 160.000s 72931.712us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 32.000s 16349.017us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 27.000s 32264.855us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 24.000s 9636.785us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 707.642us 1 1 100.00
sram_ctrl_partial_access_b2b 101.000s 9055.135us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2997.620us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 1435.053us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 677.363us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5925.035us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 691.011us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 206.000s 30178.165us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 13.813us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 125.255us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 125.255us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.889us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.571us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 50.503us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 49.736us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.889us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.571us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 50.503us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 49.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7047.690us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 912.700us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 912.700us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5925.035us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 5925.035us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.571us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 24.000s 9636.785us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 9636.785us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 9636.785us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 27.000s 32264.855us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 6045.180us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7047.690us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 5188.592us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1477.597us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1477.597us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 24.000s 9636.785us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 27.000s 32264.855us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1477.597us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1836.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.000s 1262.189us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 109977264593540737993919861558283618783439991260557128375879165354793996383140 86
UVM_INFO @ 2997619677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 7226226452706730684748727423319489617177123861985914454535182720773072385400 86
UVM_INFO @ 1435053246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 107789015679325805548115910925750447475187818384657619004960392185064059688873 86
UVM_INFO @ 677363061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---