Simulation Results: sysrst_ctrl

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.26 %
  • code
  • 90.60 %
  • assert
  • 90.04 %
  • func
  • 66.14 %
  • line
  • 95.79 %
  • branch
  • 96.48 %
  • cond
  • 93.65 %
  • toggle
  • 99.77 %
  • FSM
  • 67.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.630s 2124.711us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.120s 2475.689us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.930s 2264.574us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.510s 2321.357us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.200s 6093.636us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.070s 2038.419us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 70.930s 38882.739us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.660s 3480.104us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.220s 2115.564us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.070s 2038.419us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.660s 3480.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 58.910s 154257.261us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 21.400s 25342.128us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.010s 3199.212us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1095.520s 1809357.289us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.910s 2511.408us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.120s 2166.383us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.610s 4204.544us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.750s 2621.123us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.410s 4566.448us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 25.670s 30715.800us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 556.680s 331196.615us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.690s 2018.336us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.140s 2016.449us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.850s 2125.016us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.850s 2125.016us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.200s 6093.636us 1 1 100.00
sysrst_ctrl_csr_rw 4.070s 2038.419us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.660s 3480.104us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 23.970s 9644.670us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.200s 6093.636us 1 1 100.00
sysrst_ctrl_csr_rw 4.070s 2038.419us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.660s 3480.104us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 23.970s 9644.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 34.420s 22037.601us 1 1 100.00
sysrst_ctrl_tl_intg_err 75.590s 42409.653us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 75.590s 42409.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.770s 22424.576us 1 1 100.00