Simulation Results: uart

 
18/06/2026 15:30:44 DVSim: v1.49.9 sha: a114efe json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.03 %
  • code
  • 95.24 %
  • assert
  • 98.27 %
  • func
  • 61.58 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 94.05 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 8.460s 5680.974us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 24.555us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 39.809us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.160s 313.437us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 15.322us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.740s 34.954us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 39.809us 1 1 100.00
uart_csr_aliasing 0.800s 15.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 53.870s 117036.218us 1 1 100.00
parity 2 2 100.00
uart_smoke 8.460s 5680.974us 1 1 100.00
uart_tx_rx 53.870s 117036.218us 1 1 100.00
parity_error 2 2 100.00
uart_intr 25.190s 23523.419us 1 1 100.00
uart_rx_parity_err 16.900s 25220.336us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 53.870s 117036.218us 1 1 100.00
uart_intr 25.190s 23523.419us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 82.560s 256420.646us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 33.060s 39345.893us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.400s 160409.844us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 25.190s 23523.419us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 25.190s 23523.419us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 25.190s 23523.419us 1 1 100.00
perf 1 1 100.00
uart_perf 380.630s 14414.222us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.870s 4085.377us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.870s 4085.377us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 38.280s 89770.969us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 25.430s 30327.327us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.840s 1304.591us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 17.800s 4552.952us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 172.950s 163210.601us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 64.040s 310667.539us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.570s 46.095us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 44.839us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.900s 75.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.900s 75.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 24.555us 1 1 100.00
uart_csr_rw 0.630s 39.809us 1 1 100.00
uart_csr_aliasing 0.800s 15.322us 1 1 100.00
uart_same_csr_outstanding 0.770s 38.488us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 24.555us 1 1 100.00
uart_csr_rw 0.630s 39.809us 1 1 100.00
uart_csr_aliasing 0.800s 15.322us 1 1 100.00
uart_same_csr_outstanding 0.770s 38.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.140s 63.520us 1 1 100.00
uart_tl_intg_err 1.340s 102.279us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.340s 102.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 19.430s 2359.599us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 13361283500475528212836907055031186015821389064113484247463785231674721620985 83
UVM_ERROR @ 89434578974 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 89434828972 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (25 [0x19] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 89434900400 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 89435257540 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (25 [0x19] vs 250 [0xfa]) reg name: uart_reg_block.rdata