Simulation Results

Simulation Results: adc_ctrl

22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.87 %

code
92.78 %

assert
91.90 %

func
12.92 %

line
98.03 %

branch
96.29 %

cond
86.27 %

toggle
99.53 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		52.63%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	8.400s	5670.312us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.060s	1409.369us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.230s	484.114us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	17.380s	36709.315us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	786.858us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.300s	473.237us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.230s	484.114us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	786.858us	1	1	100.00

10/19 passed

52.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.600s	342.037us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.890s	490.136us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.700s	370.332us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.830s	480.274us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.680s	339.284us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.630s	343.822us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	0.640s	375.015us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.860s	422.010us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	5.160s	3701.788us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	56.800s	42166.993us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	37.900s	88989.221us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	2.530s	4087.861us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.850s	311.163us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.960s	366.132us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	2.170s	1011.157us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	2.170s	1011.157us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.060s	1409.369us	1	1	100.00
	adc_ctrl_csr_rw	1.230s	484.114us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	786.858us	1	1	100.00
	adc_ctrl_same_csr_outstanding	1.100s	2135.173us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.060s	1409.369us	1	1	100.00
	adc_ctrl_csr_rw	1.230s	484.114us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	786.858us	1	1	100.00
	adc_ctrl_same_csr_outstanding	1.100s	2135.173us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	5.910s	7731.030us	1	1	100.00
	adc_ctrl_tl_intg_err	11.570s	7982.352us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	11.570s	7982.352us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	8.060s	3671.760us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	6557555690053099639709996903159779946574939653248863688465884506504880189525	386	UVM_INFO @ 342037015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	31354410662208744756117362418139158011105009750897692207689221407541554558435	386	UVM_INFO @ 490136223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	33695917695674845418215266620507625576219502184405219776388966630631698386417	386	UVM_INFO @ 370332077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	77287302094991840956952604939563635573679144777474895107874073593920026874104	386	UVM_INFO @ 480274154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	13975129873761926964049731201953006250680176599805194993089658727237797748165	386	UVM_INFO @ 339284103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	63996185400193869399105672156217295840115485978893497244211130505502436613355	386	UVM_INFO @ 343822252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	4919853927263944154117764693833242477255421984112635848362751431073929026725	386	UVM_INFO @ 422009893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	53152252221461480239630040806706794703482787128474799385229451039349873834093	386	UVM_INFO @ 375015167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	65969401562769303851986896415882692877275373088506061700730698825444197010903	399	UVM_INFO @ 4087860667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---