Simulation Results: aes/unmasked

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.21 %
  • code
  • 88.81 %
  • assert
  • 97.73 %
  • func
  • 72.08 %
  • block
  • 89.09 %
  • line
  • 91.54 %
  • branch
  • 79.05 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 116.119us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 76.600us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 73.205us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 58.033us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 479.419us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 75.643us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 88.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 58.033us 1 1 100.00
aes_csr_aliasing 2.000s 75.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 76.600us 1 1 100.00
aes_config_error 2.000s 96.410us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 76.600us 1 1 100.00
aes_config_error 2.000s 96.410us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_b2b 1.000s 67.598us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 76.600us 1 1 100.00
aes_config_error 2.000s 96.410us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 90.297us 1 1 100.00
aes_config_error 2.000s 96.410us 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 1.000s 94.757us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 785.373us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_sideload 3.000s 108.857us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 277.631us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 9.000s 63.298us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 91.960us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 325.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 325.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 73.205us 1 1 100.00
aes_csr_rw 1.000s 58.033us 1 1 100.00
aes_csr_aliasing 2.000s 75.643us 1 1 100.00
aes_same_csr_outstanding 1.000s 161.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 73.205us 1 1 100.00
aes_csr_rw 1.000s 58.033us 1 1 100.00
aes_csr_aliasing 2.000s 75.643us 1 1 100.00
aes_same_csr_outstanding 1.000s 161.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 17.395us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 157.703us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 610.178us 1 1 100.00
aes_tl_intg_err 3.000s 435.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 435.598us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 76.600us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
aes_core_fi 1.000s 77.941us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 96.410us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_core_fi 1.000s 77.941us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.035us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.762us 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 107.040us 1 1 100.00
aes_sideload 3.000s 108.857us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.762us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.762us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.762us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.762us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.762us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 107.040us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 167.913us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 167.913us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 167.913us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 167.913us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 181.125us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 75.528us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 167.913us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 167.913us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 56.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 297.433us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 62417380870346744801710164240638289112701475206816711845785177504184941436120 1603
UVM_INFO @ 17395268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 86502477087093933235634802133522743240902727859258350952928211190747285675268 2896
UVM_INFO @ 63297846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 107035824870927072554578364401345843530248310613214613565361867490645229987712 402
UVM_INFO @ 297433300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 94348602191331958752078225565159975671077450669230869174855378546832997346875 6385
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_control_fi 57353011208866643976552722486821181085022347591703644232678690342358829324998 None