Simulation Results: alert_handler

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.45 %
  • code
  • 91.29 %
  • assert
  • 98.22 %
  • func
  • 78.83 %
  • line
  • 99.75 %
  • branch
  • 98.12 %
  • cond
  • 90.96 %
  • toggle
  • 86.95 %
  • FSM
  • 80.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.150s 218.137us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.360s 134.467us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 340.180s 11185.402us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 83.760s 8140.291us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.260s 1035.445us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.360s 134.467us 1 1 100.00
alert_handler_csr_aliasing 83.760s 8140.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 159.490s 61383.429us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 3.470s 196.974us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 723.650s 31689.593us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 21.860s 388.974us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 22.270s 660.780us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 38.790s 4423.378us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 143.890s 21586.098us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 509.410s 50239.594us 1 1 100.00
alert_handler_lpg_stub_clk 1691.340s 49874.851us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1570.600s 45422.446us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 17.080s 681.504us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.800s 53.900us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.060s 14.304us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.830s 324.883us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.830s 324.883us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.150s 218.137us 1 1 100.00
alert_handler_csr_rw 3.360s 134.467us 1 1 100.00
alert_handler_csr_aliasing 83.760s 8140.291us 1 1 100.00
alert_handler_same_csr_outstanding 8.990s 91.423us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.150s 218.137us 1 1 100.00
alert_handler_csr_rw 3.360s 134.467us 1 1 100.00
alert_handler_csr_aliasing 83.760s 8140.291us 1 1 100.00
alert_handler_same_csr_outstanding 8.990s 91.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 92.950s 26485.222us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 92.950s 26485.222us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 92.950s 26485.222us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 92.950s 26485.222us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 174.050s 8597.422us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
alert_handler_tl_intg_err 13.980s 341.280us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 13.980s 341.280us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 92.950s 26485.222us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 33.980s 2497.492us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.860s 388.974us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 509.410s 50239.594us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.860s 388.974us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 723.650s 31689.593us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 723.650s 31689.593us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 38.060s 1495.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 19.210s 2052.230us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 50464251387137157918813891858733845213228404688645339874010082780334472989934 120
UVM_INFO @ 21586098193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 65581608396093715387535329732425521983042656877440014801204310137852513958810 200
UVM_INFO @ 681504356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 112288567049063847606497015266092101173766115577563108184385294818589375785332 91
UVM_INFO @ 2052230231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---