Simulation Results

Simulation Results: chip

22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.04 %

code
83.95 %

assert
97.37 %

func
34.81 %

line
93.93 %

branch
92.27 %

cond
87.91 %

toggle
88.49 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		75.90%
V2S		100.00%
V3		65.38%
unmapped		54.55%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	185.830s	2767.412us	1	1	100.00
	chip_sw_example_rom	72.150s	1944.121us	1	1	100.00
	chip_sw_example_manufacturer	179.270s	3607.136us	1	1	100.00
	chip_sw_example_concurrency	187.930s	2922.748us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	297.980s	7334.983us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	526.220s	5828.061us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	345.320s	4819.899us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3104.260s	27759.701us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	630.490s	10296.667us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3104.260s	27759.701us	1	1	100.00
	chip_csr_rw	526.220s	5828.061us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.630s	54.051us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	316.860s	4619.253us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	316.860s	4619.253us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	316.860s	4619.253us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	433.310s	4367.863us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	433.310s	4367.863us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	372.260s	4575.752us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	377.380s	4410.687us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	373.490s	4346.062us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	350.830s	4666.630us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	405.150s	4831.905us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	314.990s	5003.623us	1	1	100.00

211/278 passed

75.90 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	197.770s	5611.231us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	197.770s	5611.231us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	225.840s	3197.788us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	349.840s	6328.825us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	207.780s	3498.552us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	113.900s	3431.094us	1	1	100.00
	chip_tap_straps_testunlock0	402.470s	6461.694us	1	1	100.00
	chip_tap_straps_rma	303.830s	5696.766us	1	1	100.00
	chip_tap_straps_prod	101.650s	2732.476us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	754.530s	10175.335us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	445.480s	5731.716us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	445.480s	5731.716us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	625.610s	7570.784us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1823.630s	15099.187us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	393.440s	4593.144us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	620.790s	6386.985us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	18237.922us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.810s	2482.062us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	876.030s	7576.092us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	183.390s	3614.934us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1221.710s	10217.605us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	170.790s	3352.414us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	407.000s	5444.376us	1	1	100.00
	chip_sw_clkmgr_jitter	165.950s	2932.905us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	208.610s	3745.937us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	665.150s	9429.494us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	260.510s	5577.318us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	182.630s	3266.102us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	260.510s	5577.318us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	131.900s	2622.193us	1	1	100.00
	chip_sw_aes_smoketest	192.880s	2838.882us	1	1	100.00
	chip_sw_aon_timer_smoketest	169.460s	3412.430us	1	1	100.00
	chip_sw_clkmgr_smoketest	170.790s	3526.543us	1	1	100.00
	chip_sw_csrng_smoketest	128.500s	2706.945us	1	1	100.00
	chip_sw_entropy_src_smoketest	940.020s	7290.017us	1	1	100.00
	chip_sw_gpio_smoketest	231.190s	3776.183us	1	1	100.00
	chip_sw_hmac_smoketest	198.420s	3442.296us	1	1	100.00
	chip_sw_kmac_smoketest	165.010s	2508.404us	1	1	100.00
	chip_sw_otbn_smoketest	878.520s	7413.070us	1	1	100.00
	chip_sw_pwrmgr_smoketest	286.440s	6552.066us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	210.880s	5781.033us	1	1	100.00
	chip_sw_rv_plic_smoketest	160.940s	3114.950us	1	1	100.00
	chip_sw_rv_timer_smoketest	131.130s	2731.889us	1	1	100.00
	chip_sw_rstmgr_smoketest	175.130s	2962.109us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	148.070s	3007.141us	1	1	100.00
	chip_sw_uart_smoketest	158.560s	3217.793us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	118.190s	2828.372us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	310.730s	4222.885us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8369.760s	63457.739us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3148.140s	15098.149us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	35.905s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	225.280s	3531.414us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	158.700s	3750.872us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7156.220s	55350.729us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7636.230s	57155.359us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	55.680s	2213.416us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	55.680s	2213.416us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3104.260s	27759.701us	1	1	100.00
	chip_same_csr_outstanding	1974.880s	26958.598us	1	1	100.00
	chip_csr_hw_reset	297.980s	7334.983us	1	1	100.00
	chip_csr_rw	526.220s	5828.061us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3104.260s	27759.701us	1	1	100.00
	chip_same_csr_outstanding	1974.880s	26958.598us	1	1	100.00
	chip_csr_hw_reset	297.980s	7334.983us	1	1	100.00
	chip_csr_rw	526.220s	5828.061us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	17.440s	266.009us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.690s	53.806us	1	1	100.00
	xbar_smoke_large_delays	38.860s	6887.618us	1	1	100.00
	xbar_smoke_slow_rsp	48.890s	4546.136us	1	1	100.00
	xbar_random_zero_delays	17.570s	255.750us	1	1	100.00
	xbar_random_large_delays	168.500s	28668.589us	1	1	100.00
	xbar_random_slow_rsp	235.700s	28210.866us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	37.330s	1267.865us	1	1	100.00
	xbar_error_and_unmapped_addr	5.180s	105.997us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	27.280s	548.202us	1	1	100.00
	xbar_error_and_unmapped_addr	5.180s	105.997us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	35.490s	1324.563us	1	1	100.00
	xbar_access_same_device_slow_rsp	41.980s	4380.959us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	21.610s	388.912us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	5.950s	197.236us	1	1	100.00
	xbar_stress_all_with_error	159.680s	2941.176us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	140.760s	2557.779us	1	1	100.00
	xbar_stress_all_with_reset_error	204.690s	2848.628us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3148.140s	15098.149us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2412.930s	23136.904us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	2889.230s	15327.287us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	108.837s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	20.550s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	20.529s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	50.020s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	44.897s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	137.142s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	29.115s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	23.972s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	99.646s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	31.597s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	118.220s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	67.246s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	99.338s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	36.273s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	29.299s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	21.020s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	20.690s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.730s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	22.970s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	21.510s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.820s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.260s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.780s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.250s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.380s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.600s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.550s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.230s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.350s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.680s	10.140us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	52.075s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	71.692s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	64.436s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	74.612s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	88.335s	0.000us	0	1	0.00
rom_e2e_keymgr_init				1	3	33.33
	rom_e2e_keymgr_init_rom_ext_meas	3019.830s	16712.091us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3059.590s	16602.407us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5832.500s	30586.519us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3338.950s	16305.343us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3375.980s	35233.376us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3375.980s	35233.376us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	169.880s	3552.598us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.810s	2482.062us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	150.780s	2401.816us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	189.250s	3294.549us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	915.550s	8529.182us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	202.860s	3384.503us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	318.650s	5631.064us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	556.440s	5155.900us	1	1	100.00
	chip_plic_all_irqs_10	301.960s	4225.491us	1	1	100.00
	chip_plic_all_irqs_20	449.900s	4527.210us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	164.270s	3051.297us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	911.380s	12077.186us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	322.500s	5799.085us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	124.430s	3071.481us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.160s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	915.380s	7759.796us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1093.000s	7470.174us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	832.780s	7733.477us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7961.110s	255915.342us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	241.020s	3853.227us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	286.440s	6552.066us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	241.020s	3853.227us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	390.450s	7871.780us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	390.450s	7871.780us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	329.230s	6941.237us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	374.290s	5338.996us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	600.480s	6009.745us	1	1	100.00
	chip_sw_aes_idle	189.250s	3294.549us	1	1	100.00
	chip_sw_hmac_enc_idle	151.470s	2563.466us	1	1	100.00
	chip_sw_kmac_idle	140.010s	2837.616us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	403.020s	5272.261us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	277.640s	4936.425us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	242.950s	4449.574us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	298.370s	4437.117us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	899.220s	10144.152us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	361.800s	3656.993us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	368.670s	4560.512us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	449.660s	4608.311us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	448.030s	5423.086us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	369.570s	3989.055us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	356.230s	4828.821us	1	1	100.00
	chip_sw_ast_clk_outputs	625.610s	7570.784us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	592.970s	10632.362us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	449.660s	4608.311us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	448.030s	5423.086us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	393.440s	4593.144us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	620.790s	6386.985us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	18237.922us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.810s	2482.062us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	876.030s	7576.092us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	183.390s	3614.934us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1221.710s	10217.605us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	170.790s	3352.414us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	407.000s	5444.376us	1	1	100.00
	chip_sw_clkmgr_jitter	165.950s	2932.905us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	146.650s	3170.600us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	380.940s	4468.680us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	601.160s	6904.839us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4249.020s	24779.492us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	172.600s	2963.483us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	182.610s	3019.937us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	728.060s	9058.908us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	213.780s	3775.173us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	398.710s	4923.789us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1165.330s	23376.510us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3650.240s	28268.862us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	625.610s	7570.784us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	355.970s	5123.007us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	233.440s	3162.067us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	915.380s	7759.796us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1806.070s	24068.722us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	301.090s	4493.300us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	471.310s	7679.773us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	159.580s	2922.653us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	4382.160s	24470.303us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	202.000s	3137.772us	1	1	100.00
	chip_sw_edn_entropy_reqs	795.130s	6827.574us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	202.000s	3137.772us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1806.070s	24068.722us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	181.720s	2994.329us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1501.920s	23866.857us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	637.650s	5587.610us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	620.790s	6386.985us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	353.770s	4671.889us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	393.440s	4593.144us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3652.920s	43085.735us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1501.920s	23866.857us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	237.480s	3329.364us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3652.920s	43085.735us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	296.850s	10469.583us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	579.810s	5363.965us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	461.670s	5787.945us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	461.670s	5787.945us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	175.000s	2990.803us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	183.390s	3614.934us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	151.470s	2563.466us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1544.770s	12026.934us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1666.060s	12026.416us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	392.790s	5255.233us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	372.580s	4483.173us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	396.930s	4696.832us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	351.440s	4613.909us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1221.710s	10217.605us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	817.340s	7318.388us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	915.550s	8529.182us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4411.650s	20018.664us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	116.010s	2451.503us	1	1	100.00
	chip_sw_kmac_mode_kmac	183.770s	3086.467us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	170.790s	3352.414us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
chip_sw_kmac_app_lc				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	119.610s	2962.698us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	697.040s	6170.102us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	140.010s	2837.616us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	318.650s	5631.064us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	113.900s	3431.094us	1	1	100.00
	chip_tap_straps_rma	303.830s	5696.766us	1	1	100.00
	chip_tap_straps_prod	101.650s	2732.476us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	175.680s	3134.097us	1	1	100.00
chip_sw_lc_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_lc_ctrl_transitions				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_lc_ctrl_kmac_req				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1349.810s	11169.435us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	22	81.82
	chip_sw_flash_ctrl_lc_rw_en	126.100s	3267.491us	0	1	0.00
	chip_sw_flash_rma_unlocked	3652.920s	43085.735us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	223.870s	3808.120us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	640.070s	8489.722us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	462.300s	6974.971us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	583.160s	7318.220us	0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	386.960s	9025.875us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	652.240s	8236.661us	1	1	100.00
	chip_prim_tl_access	296.850s	10469.583us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	592.970s	10632.362us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	361.800s	3656.993us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	368.670s	4560.512us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	449.660s	4608.311us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	448.030s	5423.086us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	369.570s	3989.055us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	356.230s	4828.821us	1	1	100.00
	chip_tap_straps_dev	113.900s	3431.094us	1	1	100.00
	chip_tap_straps_rma	303.830s	5696.766us	1	1	100.00
	chip_tap_straps_prod	101.650s	2732.476us	1	1	100.00
	chip_rv_dm_lc_disabled	166.910s	7289.419us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	126.160s	3121.245us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	105.540s	3131.300us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	77.490s	3331.862us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	82.160s	2927.187us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1511.290s	28187.953us	1	1	100.00
	chip_rv_dm_lc_disabled	166.910s	7289.419us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	580.400s	9841.041us	0	1	0.00
	chip_sw_lc_walkthrough_prod	683.340s	11496.615us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	591.550s	11293.607us	1	1	100.00
	chip_sw_lc_walkthrough_rma	338.480s	6363.463us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1511.290s	28187.953us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	65.800s	2108.119us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	68.430s	2291.215us	1	1	100.00
	rom_volatile_raw_unlock	33.939s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3869.920s	17314.037us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3749.500s	18237.922us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	600.480s	6009.745us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	600.480s	6009.745us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	600.480s	6009.745us	1	1	100.00
chip_sw_otbn_mem_scramble				0	1	0.00
	chip_sw_otbn_mem_scramble	351.940s	3870.661us	0	1	0.00
chip_otp_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_otp_ctrl_keys				4	5	80.00
	chip_sw_flash_init	1501.920s	23866.857us	1	1	100.00
	chip_sw_otbn_mem_scramble	351.940s	3870.661us	0	1	0.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	351.780s	4617.933us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	158.790s	3029.565us	1	1	100.00
chip_sw_otp_ctrl_entropy				4	5	80.00
	chip_sw_flash_init	1501.920s	23866.857us	1	1	100.00
	chip_sw_otbn_mem_scramble	351.940s	3870.661us	0	1	0.00
	chip_sw_keymgr_key_derivation	1070.670s	9931.728us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	351.780s	4617.933us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	158.790s	3029.565us	1	1	100.00
chip_sw_otp_ctrl_program				0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	366.670s	5047.055us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	175.680s	3134.097us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	6	66.67
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	223.870s	3808.120us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	640.070s	8489.722us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	462.300s	6974.971us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	583.160s	7318.220us	0	1	0.00
	chip_sw_lc_ctrl_transition	1201.900s	32151.498us	0	1	0.00
	chip_prim_tl_access	296.850s	10469.583us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	296.850s	10469.583us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	896.430s	7430.244us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	206.730s	6036.869us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1201.190s	29757.871us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	204.470s	7642.439us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	541.130s	9020.060us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	353.810s	5910.832us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	822.570s	23847.836us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	980.620s	15337.156us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	390.450s	7871.780us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1069.130s	11698.739us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	303.620s	4787.192us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	206.730s	6036.869us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	287.320s	4376.488us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	892.340s	15064.435us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	363.890s	7001.104us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	173.790s	3374.642us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	506.790s	11713.895us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	704.400s	6560.154us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1048.550s	13357.519us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1651.150s	28915.922us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	189.750s	2939.464us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	386.960s	9025.875us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	386.960s	9025.875us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1048.550s	13357.519us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	506.790s	11713.895us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	303.620s	4787.192us	1	1	100.00
	chip_sw_pwrmgr_smoketest	286.440s	6552.066us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	258.190s	4160.825us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	442.690s	6581.853us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	339.370s	4355.007us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	911.380s	12077.186us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	189.170s	3666.604us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1093.000s	7470.174us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	508.330s	5310.769us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	483.110s	4374.068us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	197.230s	3081.735us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	158.790s	3029.565us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	442.690s	6581.853us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	442.690s	6581.853us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	159.400s	2926.449us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	536.880s	8448.706us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	841.020s	13663.334us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	258.190s	4160.825us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	167.730s	3114.160us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	294.860s	6200.705us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	303.830s	5696.766us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	166.910s	7289.419us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	556.440s	5155.900us	1	1	100.00
	chip_plic_all_irqs_10	301.960s	4225.491us	1	1	100.00
	chip_plic_all_irqs_20	449.900s	4527.210us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	174.360s	2844.799us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	161.450s	3623.924us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3148.140s	15098.149us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	434.640s	6694.461us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	181.830s	3735.264us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	200.820s	3172.278us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	191.730s	2996.932us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	351.780s	4617.933us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	407.000s	5444.376us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	366.290s	7591.279us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	536.820s	8109.486us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	652.240s	8236.661us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
	chip_sw_data_integrity_escalation	445.480s	5731.716us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	704.400s	6560.154us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1055.110s	22057.726us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	200.080s	3038.877us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	236.970s	4128.317us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	355.440s	5062.102us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1055.110s	22057.726us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1055.110s	22057.726us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2271.620s	20078.564us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2271.620s	20078.564us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	354.910s	7326.562us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3375.980s	35233.376us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	130.660s	2573.506us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	190.810s	3230.005us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	319.650s	3816.660us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	325.820s	3734.902us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	924.420s	8505.326us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5127.660s	31749.806us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1917.060s	12785.792us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	220.000s	3106.053us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	171.890s	3060.894us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	144.660s	2809.203us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9833.450s	72018.708us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1155.880s	6837.460us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	506.360s	6541.037us	0	1	0.00
	rom_e2e_jtag_debug_dev	176.470s	4409.538us	0	1	0.00
	rom_e2e_jtag_debug_rma	207.860s	4684.499us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	88.760s	3355.020us	0	1	0.00
	rom_e2e_jtag_inject_dev	222.510s	5261.648us	0	1	0.00
	rom_e2e_jtag_inject_rma	98.390s	2992.602us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	105.271s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	265.060s	3960.376us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	342.450s	2949.914us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	461.890s	3965.279us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1513.170s	11494.101us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	231.200s	2856.984us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	606.270s	5344.171us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	86.570s	2501.161us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	194.190s	3560.470us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	344.570s	5344.546us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	246.980s	4403.263us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1048.550s	13357.519us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	506.360s	6541.037us	0	1	0.00
	rom_e2e_jtag_debug_dev	176.470s	4409.538us	0	1	0.00
	rom_e2e_jtag_debug_rma	207.860s	4684.499us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	389.750s	6571.721us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	475.450s	6162.866us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5670.860s	38450.749us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5670.860s	38450.749us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	155.490s	3621.625us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	433.310s	4367.863us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3218.130s	19118.147us	1	1	100.00

unmapped

6/11 passed

54.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				6	11	54.55
	chip_sival_flash_info_access	196.140s	3035.732us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	19.410s	10.280us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.640s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	154.060s	2666.832us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	190.440s	3498.632us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	200.090s	3592.636us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.045s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	185.690s	3504.407us	1	1	100.00
	ate_bootstrap_flash_erase	676.770s	10010.360us	0	1	0.00
	ate_bootstrap_one_frame	6462.500s	44991.106us	1	1	100.00
	ate_bootstrap_disjoint	9983.410s	84706.472us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	114774647589924683357986360903422865901594369403860973941669032507717367213546	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	48399438492628259470918840498720179559825731434044405636756130559866821337364	None	Another command (pid=470593) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=551569) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=408244) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	63684312355130603155060974367508779736157691603900625827106041136614958949332	None	Another command (pid=579557) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	107949150190629415799591495719862853349056172303449381910102448384229853971239	None	Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=569591) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	23881120580518394812608617197630319194119009390307957318398075463409242291290	None	Another command (pid=658454) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=653556) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=639291) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	46349172539410004937684323868462945796878531083433744263008861206358975260438	None	Another command (pid=658454) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=653556) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=639291) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	32127715487775231538227143112147509098954662779200004302150070806986951361894	None	Another command (pid=579557) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	95940447303640377159470536841033191564741600483643076198633046542909475764120	None	Another command (pid=603499) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=606160) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=606897) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	57287761540637229712642011750660567523604047778909679464284992663805664602512	None	Another command (pid=579557) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	58713584415306566150493151693973301465623478389203040647469241182089345623697	None	Another command (pid=760356) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=728662) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=743028) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	62746938442936131312624761155942696256580446230521701317777936081230781150579	None	Another command (pid=568416) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=610657) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=607487) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	49157174606032128756178188018376200240431184855651375512166585353050725949194	None	Another command (pid=425381) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=507861) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=455725) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	44623545870890928931889544371265328034232453590614339280964240022641803035213	None	Another command (pid=425381) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=507861) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=455725) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	61790725335051522090370380055648821182843791854412551993458625035818705945389	None	Another command (pid=679620) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=679211) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=681054) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	36044736261476915795978118947726139935334508787512063677450428388886633854030	None	Another command (pid=556064) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=569973) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=456343) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	34427969075293231822247273818484443352899161471006230561003075886917055136123	None	Another command (pid=579557) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	21442049975846186468170054202760163804769044311671917666202870295520483827389	None	Another command (pid=438359) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=454075) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=455211) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	104792464979589562867542822629331351452878285034919712094117126047292608123246	None	Another command (pid=507861) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=458417) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=455725) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	13068878511754940520359848190496869579906656565443439119110384194130347481373	None	Another command (pid=457196) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=474794) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=451251) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	764716970464212830592225621478277423802521785120586776594466149668156829807	None	Another command (pid=527870) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=409796) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=430828) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	54772915029617603386498646562262740155352437319955478273928372114951316651894	None	Another command (pid=579557) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=592613) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=593807) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	72409705196461302016143768577939566879008590904461653241848702006898949247189	None	---- STDERR ---- Another command (pid=368484) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=411956) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	58080636392473692065256590426926711666140782733495091312091873067628863742710	None	Another command (pid=415478) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=382595) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=432128) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	110307633617731503391060716490959093380378418062605657620652740460903805804283	None	Another command (pid=451251) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=470593) is running. Waiting for it to complete on the server (server_pid=283548)... Another command (pid=551569) is running. Waiting for it to complete on the server (server_pid=283548)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	115012114042354808669256549569787785629504592295060310980746673702092795423416	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	18552905008228197657795561752522947642510486640666446276286288371654558658691	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	25772154485309684214739864798349989476129261215112895164985088351285438312611	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	55225030998644127166144972356031010432614517648513824754398209342915832044482	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	96074729375175742514939132848997017938921966666877759433858470949856210501939	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	110682102113492295783815268399602469510584698082937240752700440414836139640592	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	82600274463001174511836674084945584419593861093245441316160555511745515705965	366	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	49571275506760343170120385872521974292857326551073866596835317622454474373611	368	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	26831458804113528242281318252598193095539424421303093531823487400186034303235	364	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	83243302917728260793893015611075522760211916425287801719908251794202108267872	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	49459103619174629669155037864280754701670684073501908495846934008202219437525	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	4516414547261241587276399313031895156967198418762817019305803983612747118855	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	37807190073853076420554040667947536615670159122513677935584640629074075367465	369	UVM_INFO @ 9841.041224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	27134239458786440046043237827571586853323191806761832576685020491457331697722	369	UVM_INFO @ 11496.615320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	109425950866226953919328707158958748735979574757278890622896928336655601514949	341	UVM_INFO @ 6363.463048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	49541409871879267219716131159466220520878696905112470509434530799118386281804	344	UVM_ERROR @ 11713.895000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 11713.895000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	20289860805891774152968841598285938707752601171563783603331901414635180408002	354	UVM_ERROR @ 15064.435000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 15064.435000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	86312760108990181781484781807993145647202804304388977705816141218091522320107	319	UVM_ERROR @ 7871.780000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7871.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	20942888181123603150500632645655046708475817001005104073818550043234658988237	310	UVM_INFO @ 12026.933699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	93195821752696529321862264153502923915286877581828383717182261547406515448407	310	UVM_INFO @ 12026.415991 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	108670602567977684084390810072846211273445366046886306373578455975183821292196	336	UVM_INFO @ 20018.664077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	70901120414328483805684027653579750972671814730398801230243567617825441028145	327	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	64836349383900950666632101153584866779143730624224762360208766083976137484463	326	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	13190517035231356849353294451721113407244158123628297735306574316198850441785	326	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	76855360889449823766002976143423078648940277736490444158179829444905923012388	368	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15643999420165248438656794313427316800806987728229896223211252624864675329723	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	11079286212876752078130803023080272112453544275150261863130091156420160754740	365	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	10323851606493004525537612314622707536271165445855686680988469329887539907700	328	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	86714448480994297123012489734847643109587574810111065841445902250296002413624	301	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	27070173585742415906947833321389264463618140682192485010713682780578172648867	451	UVM_INFO @ 3197.788000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	60556317715723122576515621789951780764017808962913684129031941966962789045888	327	UVM_INFO @ 3735.263600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	91990785785982749464894546071019654014750117344127405710256974077780511393678	309	UVM_INFO @ 3267.491211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	114837017652487747237131607726059007924455258527849908266230677365543849693279	342	UVM_INFO @ 7318.220149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	85443358518456651294748113966165863895808288716720652358856708438078436029812	316	UVM_ERROR @ 3560.470476 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3560.470476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	90660789479334427561982919945138810554867885043946821718142605874908048390409	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_transition	74796193971959389691857580327556533460851093800975629239656064182213036346530	347	UVM_INFO @ 32151.497664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	103493777518588738438359372226129065756864444345537775614126662957597324391826	322	UVM_ERROR @ 6036.868856 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 6036.868856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	102109041657371146232970838721730842320250995521600470244586617416910159374627	313	UVM_ERROR @ 3374.642274 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3374.642274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	108857707146507349052174474344338472235739644541679753229325859938285853438162	332	UVM_INFO @ 35233.375786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:260)] CHECK-fail: Expecting at least * DMEM integrity errors, got *				1 test run
	chip_sw_otbn_mem_scramble	47373647602669093078641929730552931595388264424072212958846065465670275388802	310	UVM_INFO @ 3870.660520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:302)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	97323597223655742201171626319595007304523077794347793603418351747803621433626	307	UVM_INFO @ 3384.502824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	101281912128194459208922947492983401836928906061974958044707106893267701789614	308	UVM_INFO @ 3071.480524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	103817974040662797752292893186419961075678986022199586154661597237426162340084	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	10746719034949399185088887094188923063719110962908617883749862838570340523760	217	TL item was: req: (cip_tl_seq_item@35548) { a_addr: 'h1056c a_data: 'hcca7bffb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h1baef d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2213.416234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	81518870133496529176170493289988492674966525369264555760655946269328089649700	343	UVM_INFO @ 3960.375642 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()				1 test run
	chip_sw_pwrmgr_lowpower_cancel	52035901546515672348638916337954595912848372721396647183160536253698938721843	311	UVM_INFO @ 3592.635985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	61072221943865962249797495559400133292770487428360994436346344711706460973251	265	UVM_INFO @ 7289.419368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_idle_load	68564738524936621601608584638477391724183243310669933497252902045355348390945	312	UVM_INFO @ 3531.414500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *				1 test run
	chip_sw_power_sleep_load	38069095989848161779543355474984553217026211066853372122359611383281378528618	319	UVM_INFO @ 3750.872000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	53491226829481927979926271745033942586913405733340722394687658730590039331176	327	UVM_INFO @ 15099.187300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	83555809837677335481662452869534991873604787781385908864055614580862480489413	272	UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	106218431135699854761076573190609539623441960635652762652541797847436451068474	326	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	57186848145380768229910527557580236159531596204713050470343821004934799825867	326	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [] vs [*])				1 test run
	rom_e2e_jtag_debug_dev	27152468735975845097693094603752262932483998425484915615446746878497683448217	317	UVM_INFO @ 4409.537678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_meas	41656425228326725259319306157763969730611918733617769163197514271244692918418	319	UVM_INFO @ 16712.091312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	49432688327392398668376707822860437571536897227431434280152163403572592427609	319	UVM_INFO @ 16602.407384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	795590095342871591230996794397539368413281471623705675552167509062570053566	327	UVM_ERROR @ 4222.885016 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4222.885016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---