Simulation Results: clkmgr

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.95 %
  • code
  • 98.11 %
  • assert
  • 93.36 %
  • func
  • 84.39 %
  • line
  • 99.12 %
  • branch
  • 98.85 %
  • cond
  • 92.90 %
  • toggle
  • 99.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 18.737us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 28.695us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.840s 1064.137us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.520s 76.573us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.000s 25.586us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
clkmgr_csr_aliasing 1.520s 76.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.740s 52.127us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.770s 44.899us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.760s 28.439us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.840s 15.554us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 18.737us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.440s 200.513us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.920s 747.260us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.440s 200.513us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 34.530s 11428.328us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.740s 30.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.590s 119.450us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.590s 119.450us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.695us 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
clkmgr_csr_aliasing 1.520s 76.573us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 191.644us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.695us 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
clkmgr_csr_aliasing 1.520s 76.573us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 191.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.400s 712.529us 1 1 100.00
clkmgr_tl_intg_err 39.120s 10007.993us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.280s 74.877us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.280s 74.877us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.280s 74.877us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.280s 74.877us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 6.920s 2119.584us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 39.120s 10007.993us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.440s 200.513us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.920s 747.260us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.280s 74.877us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.870s 37.447us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.970s 119.664us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.840s 69.643us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.890s 82.772us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.020s 57.827us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.400s 712.529us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 16.563us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.400s 712.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.140s 254.329us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 9.070s 900.198us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 12650650032822155777562897686473264218130458033569037304615984206774116092419 75
UVM_INFO @ 2119583544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))' 1 test run
clkmgr_stress_all_with_rand_reset 73334640164190334604763341847159081444490962843944736158314328233040680803556 251
UVM_ERROR @ 900197776 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
UVM_INFO @ 900197776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 103193508764518061128477203353897860101415720223881186358582073611984437028911 93
UVM_INFO @ 10007993410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---