Simulation Results: csrng

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.58 %
  • code
  • 92.26 %
  • assert
  • 94.54 %
  • func
  • 66.94 %
  • block
  • 96.89 %
  • line
  • 97.73 %
  • branch
  • 92.35 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 45.042us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 16.899us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 65.027us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 6.000s 84.359us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 30.597us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 28.951us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 65.027us 1 1 100.00
csrng_csr_aliasing 3.000s 30.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 312.609us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 84.754us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 84.754us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 57.000s 1380.383us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 22.728us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 19.037us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 115.144us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 115.144us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 16.899us 1 1 100.00
csrng_csr_rw 3.000s 65.027us 1 1 100.00
csrng_csr_aliasing 3.000s 30.597us 1 1 100.00
csrng_same_csr_outstanding 3.000s 154.203us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 16.899us 1 1 100.00
csrng_csr_rw 3.000s 65.027us 1 1 100.00
csrng_csr_aliasing 3.000s 30.597us 1 1 100.00
csrng_same_csr_outstanding 3.000s 154.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
csrng_tl_intg_err 3.000s 87.999us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 2.487us 0 1 0.00
csrng_csr_rw 3.000s 65.027us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 312.609us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 57.000s 1380.383us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 312.609us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 57.000s 1380.383us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 312.609us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 87.999us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
csrng_sec_cm 2.000s 135.928us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 152.347us 1 1 100.00
csrng_err 2.000s 24.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 176.000s 5171.771us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 61832288733864841095771840749963309288938139424624847904642068601807187625817 100
UVM_INFO @ 84754035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 102889371172867945924107316010220267733857084855099748082644335189161834686123 99
UVM_INFO @ 2486742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 21777738977694396423091251023666481708405995321866368656422509953176496640566 372
UVM_INFO @ 5171771333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---