Simulation Results: edn/edn0

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.36 %
  • code
  • 83.20 %
  • assert
  • 96.31 %
  • func
  • 79.56 %
  • line
  • 97.77 %
  • branch
  • 92.61 %
  • cond
  • 87.87 %
  • toggle
  • 87.21 %
  • FSM
  • 50.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.920s 35.095us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 67.492us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 21.254us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.100s 651.755us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 99.919us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.280s 40.365us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 21.254us 1 1 100.00
edn_csr_aliasing 0.970s 99.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.640s 75.346us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.640s 75.346us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.640s 75.346us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 22.621us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 23.897us 1 1 100.00
errs 1 1 100.00
edn_err 0.870s 29.934us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 18.768us 1 1 100.00
edn_disable_auto_req_mode 1.170s 132.029us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.900s 282.037us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.880s 32.688us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 59.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.830s 82.591us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.830s 82.591us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 67.492us 1 1 100.00
edn_csr_rw 0.810s 21.254us 1 1 100.00
edn_csr_aliasing 0.970s 99.919us 1 1 100.00
edn_same_csr_outstanding 1.250s 38.134us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 67.492us 1 1 100.00
edn_csr_rw 0.810s 21.254us 1 1 100.00
edn_csr_aliasing 0.970s 99.919us 1 1 100.00
edn_same_csr_outstanding 1.250s 38.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
edn_tl_intg_err 1.910s 365.949us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 17.834us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 23.897us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 23.897us 1 1 100.00
edn_sec_cm 3.360s 996.803us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 23.897us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.910s 365.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 39.770s 7057.331us 1 1 100.00