Simulation Results: edn/edn1

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.30 %
  • code
  • 82.80 %
  • assert
  • 98.44 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.23 %
  • toggle
  • 86.71 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 18.068us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 19.173us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 18.310us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.430s 282.806us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 46.031us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.970s 23.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 18.310us 1 1 100.00
edn_csr_aliasing 1.240s 46.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.150s 48.176us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.150s 48.176us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.150s 48.176us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.750s 39.313us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 29.170us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 114.389us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 104.534us 1 1 100.00
edn_disable_auto_req_mode 0.970s 44.681us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.020s 348.444us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 15.728us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.880s 23.407us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.610s 402.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.610s 402.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.173us 1 1 100.00
edn_csr_rw 0.830s 18.310us 1 1 100.00
edn_csr_aliasing 1.240s 46.031us 1 1 100.00
edn_same_csr_outstanding 1.020s 24.876us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 19.173us 1 1 100.00
edn_csr_rw 0.830s 18.310us 1 1 100.00
edn_csr_aliasing 1.240s 46.031us 1 1 100.00
edn_same_csr_outstanding 1.020s 24.876us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
edn_tl_intg_err 1.300s 181.975us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 30.363us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 29.170us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 29.170us 1 1 100.00
edn_sec_cm 2.180s 160.528us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 29.170us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 181.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.520s 3444.247us 1 1 100.00