Simulation Results: flash_ctrl

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 94.36 %
  • assert
  • 96.85 %
  • func
  • 95.45 %
  • line
  • 95.96 %
  • branch
  • 97.14 %
  • cond
  • 93.71 %
  • toggle
  • 97.23 %
  • FSM
  • 87.76 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 54.840s 84.935us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.520s 49.893us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.340s 20.893us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 51.220s 3524.344us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 38.340s 3156.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.530s 56.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
flash_ctrl_csr_aliasing 38.340s 3156.816us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.480s 106.463us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.980s 17.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.850s 57.273us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 34.340s 52.873us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1167.720s 83974.802us 1 1 100.00
flash_ctrl_hw_rma_reset 521.520s 90154.978us 1 1 100.00
flash_ctrl_lcmgr_intg 11.570s 50.001us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1438.890s 251245.937us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 110.750s 162.977us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 114.850s 15986.866us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1873.470s 207418.291us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.230s 380.689us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.660s 31.933us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.080s 31.345us 1 1 100.00
flash_ctrl_re_evict 20.150s 445.907us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 152.960s 934.141us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 152.960s 934.141us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 230.340s 29627.662us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.870s 2237.055us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 36.630s 37.457us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 322.270s 3610.688us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 361.150s 1941.152us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1117.740s 2259.131us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.390s 79.469us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 132.620s 4689.752us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 14.090s 58.517us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.310s 16.681us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 124.790s 790.233us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 67.610s 19077.864us 1 1 100.00
flash_ctrl_otp_reset 43.920s 74.323us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1167.720s 83974.802us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 81.170s 938.615us 0 1 0.00
flash_ctrl_intr_wr 51.800s 2584.850us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 123.030s 8961.365us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 168.270s 69512.485us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.850s 4173.026us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.630s 3388.628us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.500s 56.025us 1 1 100.00
flash_ctrl_ro_derr 115.230s 852.924us 1 1 100.00
flash_ctrl_rw_derr 116.270s 2803.582us 1 1 100.00
flash_ctrl_derr_detect 104.530s 1691.358us 1 1 100.00
flash_ctrl_integrity 372.240s 50994.431us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.330s 165.961us 1 1 100.00
flash_ctrl_ro_serr 90.810s 3109.971us 1 1 100.00
flash_ctrl_rw_serr 123.060s 2725.655us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 57.060s 1257.289us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 42.570s 1777.418us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 111.450s 3313.427us 1 1 100.00
flash_ctrl_write_word_sweep 6.910s 94.760us 1 1 100.00
flash_ctrl_read_word_sweep 6.850s 172.511us 1 1 100.00
flash_ctrl_ro 70.680s 1964.606us 1 1 100.00
flash_ctrl_rw 368.320s 9239.080us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.390s 2417.351us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 585.830s 84352.668us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 48.040s 10037.006us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.250s 102.704us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.190s 57.756us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.850s 134.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.850s 134.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.340s 20.893us 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
flash_ctrl_csr_aliasing 38.340s 3156.816us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.980s 165.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.340s 20.893us 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
flash_ctrl_csr_aliasing 38.340s 3156.816us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.980s 165.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 31.240s 97.288us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
flash_ctrl_tl_intg_err 406.010s 699.083us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 406.010s 699.083us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 406.010s 699.083us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.530s 241.566us 1 1 100.00
flash_ctrl_wr_intg 6.750s 137.510us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 54.840s 84.935us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 43.920s 74.323us 1 1 100.00
flash_ctrl_disable 14.090s 58.517us 1 1 100.00
flash_ctrl_sec_info_access 46.180s 4355.366us 1 1 100.00
flash_ctrl_connect 7.310s 16.681us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.250s 41.952us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.720s 91.348us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.590s 78.110us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 14.090s 58.517us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.530s 241.566us 1 1 100.00
flash_ctrl_access_after_disable 6.260s 23.116us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.770s 41.075us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 14.090s 58.517us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.870s 2237.055us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 368.320s 9239.080us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 123.060s 2725.655us 1 1 100.00
flash_ctrl_rw_derr 116.270s 2803.582us 1 1 100.00
flash_ctrl_integrity 372.240s 50994.431us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1167.720s 83974.802us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.840s 749.503us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.060s 76.673us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.490s 23.548us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1739.640s 1527.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.730s 196.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 72.730s 665.718us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *e3b9c9_911efab8:ffffffff_911efab* mismatch!! 1 test run
flash_ctrl_intr_rd 24813200641835976433796067543093256518004481588560366168256772302013148308207 108
UVM_INFO @ 938615.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---