Simulation Results: hmac

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.69 %
  • code
  • 97.12 %
  • assert
  • 97.60 %
  • func
  • 44.34 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.980s 2406.416us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 133.609us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.970s 57.234us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.680s 750.741us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.630s 709.223us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.030s 86.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.970s 57.234us 1 1 100.00
hmac_csr_aliasing 2.630s 709.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 74.390s 8232.749us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.410s 2674.894us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 206.850s 9767.414us 1 1 100.00
hmac_test_sha384_vectors 19.820s 317.361us 1 1 100.00
hmac_test_sha512_vectors 413.710s 18110.436us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 316.479us 1 1 100.00
hmac_test_hmac384_vectors 11.340s 474.825us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 468.733us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.240s 1981.515us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 350.650s 34122.046us 1 1 100.00
error 1 1 100.00
hmac_error 33.340s 1101.655us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 106.860s 3704.470us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.980s 2406.416us 1 1 100.00
hmac_long_msg 74.390s 8232.749us 1 1 100.00
hmac_back_pressure 21.410s 2674.894us 1 1 100.00
hmac_datapath_stress 350.650s 34122.046us 1 1 100.00
hmac_burst_wr 15.240s 1981.515us 1 1 100.00
hmac_stress_all 9.000s 1119.493us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.980s 2406.416us 1 1 100.00
hmac_long_msg 74.390s 8232.749us 1 1 100.00
hmac_back_pressure 21.410s 2674.894us 1 1 100.00
hmac_datapath_stress 350.650s 34122.046us 1 1 100.00
hmac_wipe_secret 106.860s 3704.470us 1 1 100.00
hmac_test_sha256_vectors 206.850s 9767.414us 1 1 100.00
hmac_test_sha384_vectors 19.820s 317.361us 1 1 100.00
hmac_test_sha512_vectors 413.710s 18110.436us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 316.479us 1 1 100.00
hmac_test_hmac384_vectors 11.340s 474.825us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 468.733us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.980s 2406.416us 1 1 100.00
hmac_long_msg 74.390s 8232.749us 1 1 100.00
hmac_back_pressure 21.410s 2674.894us 1 1 100.00
hmac_datapath_stress 350.650s 34122.046us 1 1 100.00
hmac_burst_wr 15.240s 1981.515us 1 1 100.00
hmac_error 33.340s 1101.655us 1 1 100.00
hmac_wipe_secret 106.860s 3704.470us 1 1 100.00
hmac_test_sha256_vectors 206.850s 9767.414us 1 1 100.00
hmac_test_sha384_vectors 19.820s 317.361us 1 1 100.00
hmac_test_sha512_vectors 413.710s 18110.436us 1 1 100.00
hmac_test_hmac256_vectors 8.360s 316.479us 1 1 100.00
hmac_test_hmac384_vectors 11.340s 474.825us 1 1 100.00
hmac_test_hmac512_vectors 12.770s 468.733us 1 1 100.00
hmac_stress_all 9.000s 1119.493us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 9.000s 1119.493us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 18.068us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 47.616us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.710s 69.454us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.710s 69.454us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 133.609us 1 1 100.00
hmac_csr_rw 0.970s 57.234us 1 1 100.00
hmac_csr_aliasing 2.630s 709.223us 1 1 100.00
hmac_same_csr_outstanding 1.140s 43.706us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 133.609us 1 1 100.00
hmac_csr_rw 0.970s 57.234us 1 1 100.00
hmac_csr_aliasing 2.630s 709.223us 1 1 100.00
hmac_same_csr_outstanding 1.140s 43.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.800s 68.002us 1 1 100.00
hmac_tl_intg_err 3.270s 547.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.270s 547.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.980s 2406.416us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.780s 60.315us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 164.850s 8311.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.870s 100.965us 1 1 100.00