Simulation Results

Simulation Results: i2c

22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.13 %

code
81.21 %

assert
97.25 %

func
79.92 %

line
96.41 %

branch
92.33 %

cond
85.08 %

toggle
88.19 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	38.650s	1498.867us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	23.210s	1850.423us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.860s	41.146us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.790s	142.508us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.110s	682.977us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.720s	391.010us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.910s	81.683us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.790s	142.508us	1	1	100.00
	i2c_csr_aliasing	1.720s	391.010us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.670s	33.875us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	309.080s	47987.479us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	899.490s	48272.683us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.710s	28.119us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	87.550s	6145.235us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	46.980s	2796.698us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.150s	280.759us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.180s	1890.655us	1	1	100.00
	i2c_host_fifo_reset_rx	3.100s	345.163us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	81.800s	2529.605us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.410s	467.241us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.040s	70.660us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.050s	1158.891us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	466.270s	62579.287us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.360s	1014.035us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.420s	1339.408us	1	1	100.00
	i2c_target_intr_smoke	3.320s	2658.351us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.460s	259.342us	1	1	100.00
	i2c_target_fifo_reset_tx	1.600s	278.314us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	258.820s	53548.248us	1	1	100.00
	i2c_target_stress_rd	12.420s	1339.408us	1	1	100.00
	i2c_target_intr_stress_wr	3.800s	8236.920us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.190s	5448.384us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	12.420s	4050.595us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.260s	1074.406us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	17.040s	10131.758us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.850s	743.840us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.930s	139.701us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	899.490s	48272.683us	1	1	100.00
	i2c_host_perf_precise	1.470s	231.627us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.410s	467.241us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.660s	58.813us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.660s	573.081us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.960s	486.261us	1	1	100.00
	i2c_target_nack_txstretch	1.450s	160.848us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.520s	553.956us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.600s	469.126us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.670s	27.072us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.700s	42.049us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.600s	143.050us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.600s	143.050us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.860s	41.146us	1	1	100.00
	i2c_csr_rw	0.790s	142.508us	1	1	100.00
	i2c_csr_aliasing	1.720s	391.010us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	213.235us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.860s	41.146us	1	1	100.00
	i2c_csr_rw	0.790s	142.508us	1	1	100.00
	i2c_csr_aliasing	1.720s	391.010us	1	1	100.00
	i2c_same_csr_outstanding	1.130s	213.235us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.330s	69.321us	1	1	100.00
	i2c_sec_cm	0.900s	73.264us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.330s	69.321us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	9.750s	333.437us	1
target_error_intr				1
	i2c_target_unexp_stop	1.170s	521.452us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.990s	1338.545us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	94221260711325892311950388441979791372859982676976725516731212582767969238273	80	UVM_INFO @ 33875393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	70246606313156078954026549121772313893707070495210664699353936155115209311144	115	UVM_INFO @ 1338545084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_stress_all	12030850602574042682683666885749332878847248560720525883948820242096362903937	137	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @2623320
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	104668305938002554840536460495427927070962851611930408191506114862109642822254	84	UVM_INFO @ 1158890857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	34989203829243394563143188183851476176819425703606715942713355160591783155956	78	UVM_INFO @ 521452486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	59933741748717597919225883286243135537944390605345417000500809848539726417421	79	UVM_INFO @ 10131757572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	14066012241579637674426130770756500403618665772242760442741078550465955054939	85	UVM_INFO @ 333436919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	101809252117771017535826901947551022942195045946452001893239367377599446268838	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------