Simulation Results: keymgr

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.74 %
  • code
  • 94.34 %
  • assert
  • 97.49 %
  • func
  • 62.40 %
  • line
  • 98.72 %
  • branch
  • 97.63 %
  • cond
  • 93.96 %
  • toggle
  • 95.36 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.760s 90.561us 1 1 100.00
random 1 1 100.00
keymgr_random 4.610s 473.038us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.920s 49.066us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 14.070s 10059.394us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.910s 425.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.850s 206.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
keymgr_csr_aliasing 3.910s 425.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 5.420s 1038.164us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.400s 3357.228us 1 1 100.00
keymgr_sideload_kmac 12.600s 2939.852us 1 1 100.00
keymgr_sideload_aes 42.630s 6149.240us 1 1 100.00
keymgr_sideload_otbn 2.980s 102.494us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.070s 601.636us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.060s 603.208us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.780s 125.908us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.960s 316.168us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 204.173us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.860s 233.393us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 47.910s 3735.722us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.760s 11.312us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.830s 68.121us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.180s 166.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.180s 166.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.920s 49.066us 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
keymgr_csr_aliasing 3.910s 425.910us 1 1 100.00
keymgr_same_csr_outstanding 1.480s 305.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.920s 49.066us 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
keymgr_csr_aliasing 3.910s 425.910us 1 1 100.00
keymgr_same_csr_outstanding 1.480s 305.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
keymgr_tl_intg_err 3.380s 188.118us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.410s 333.989us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.410s 333.989us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.410s 333.989us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.410s 333.989us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.720s 148.310us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 3.380s 188.118us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.410s 333.989us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 5.420s 1038.164us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.610s 473.038us 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.610s 473.038us 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.610s 473.038us 1 1 100.00
keymgr_csr_rw 1.150s 27.593us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.060s 603.208us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 204.173us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.280s 204.173us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.610s 473.038us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 5.470s 389.321us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.390s 152.689us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.060s 603.208us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.390s 152.689us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.390s 152.689us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.390s 152.689us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.900s 8658.034us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.390s 152.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 2.320s 126.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_scoreboard.sv:546) [scoreboard] Check failed item.d_data == addr_phase_cfg_regwen (* [*] vs * [*]) 1 test run
keymgr_stress_all_with_rand_reset 5973407113388266202981355664585075226454059407021843713253515987069535894491 196
UVM_INFO @ 125999892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---