| V1 |
|
100.00% |
| V2 |
|
75.86% |
| V2S |
|
87.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 16.220s | 557.389us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 1.070s | 42.812us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 1.310s | 129.426us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 11.950s | 473.805us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 8.630s | 483.216us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 2.350s | 304.868us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 1.310s | 129.426us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 8.630s | 483.216us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.870s | 35.290us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 1.260s | 59.084us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 1250.840s | 87901.016us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 458.050s | 33663.106us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 31.730s | 6261.725us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 1352.180s | 147600.042us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 17.970s | 2332.421us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 11.210s | 368.655us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 187.960s | 152724.370us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 98.760s | 8598.973us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 1.890s | 68.847us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 1.640s | 87.400us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 23.600s | 2069.789us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 9.510s | 2377.126us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 7.410s | 467.072us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 0.740s | 37.359us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| kmac_error | 31.130s | 3532.577us | 0 | 1 | 0.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 0.960s | 39.211us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 1.020s | 14.066us | 0 | 1 | 0.00 | |
| edn_timeout_error | 1 | 1 | 100.00 | |||
| kmac_edn_timeout_error | 3.520s | 232.567us | 1 | 1 | 100.00 | |
| entropy_mode_error | 1 | 1 | 100.00 | |||
| kmac_entropy_mode_error | 9.460s | 433.733us | 1 | 1 | 100.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 1.100s | 53.834us | 0 | 1 | 0.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.360s | 57.765us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| kmac_stress_all | 886.030s | 189294.554us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 1.080s | 45.228us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.850s | 63.943us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 3.060s | 567.873us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 3.060s | 567.873us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 1.070s | 42.812us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 1.310s | 129.426us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 8.630s | 483.216us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.180s | 233.397us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 1.070s | 42.812us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 1.310s | 129.426us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 8.630s | 483.216us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.180s | 233.397us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.050s | 49.672us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.050s | 49.672us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.050s | 49.672us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.050s | 49.672us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 4.010s | 4381.273us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| kmac_sec_cm | 50.290s | 11149.693us | 1 | 1 | 100.00 | |
| kmac_tl_intg_err | 2.040s | 220.767us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 2.040s | 220.767us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.360s | 57.765us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 16.220s | 557.389us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 23.600s | 2069.789us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.050s | 49.672us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 50.290s | 11149.693us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 50.290s | 11149.693us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 50.290s | 11149.693us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 16.220s | 557.389us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.360s | 57.765us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 50.290s | 11149.693us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 3.000s | 179.328us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 16.220s | 557.389us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 26.560s | 1535.499us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] | 6 test runs | |||
| kmac_sideload_invalid | 60561882129903115631125560014862669131256542175345007207246409004087933490721 | 76 |
UVM_INFO @ 14066478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app | 101032971500528618736440357300593500353143372829496247342625675822037214587353 | 81 |
UVM_INFO @ 2377126254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app_with_partial_data | 10534991713614734332098099710021052613315396970271846349423652036951311878608 | 80 |
UVM_INFO @ 467071599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_refresh | 49922779018896424989737523289328166575611882062435697058292496581633266482490 | 77 |
UVM_INFO @ 37359346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_error | 77277487005568601055699174725829915579007531060021519474054896858455580948368 | 98 |
UVM_INFO @ 3532576956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_ready_error | 58583391115966199818674848355840590025379052734325892407578818883949454880795 | 77 |
UVM_INFO @ 53834348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) | 2 test runs | |||
| kmac_mubi | 19139481515591323138836960039095607441873476256839322801019280906311823400217 | 78 |
UVM_INFO @ 179327739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all_with_rand_reset | 74455047023802906930972411430686783594645878410827127019287236114167329757790 | 137 |
UVM_INFO @ 1535498852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' | 1 test run | |||
| kmac_key_error | 189009311014719543598100601796812734116655207194657964832626428749905131351 | 78 |
UVM_ERROR @ 39211028 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 39211028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|