Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.00 %
  • code
  • 83.72 %
  • assert
  • 94.97 %
  • func
  • 94.31 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.22 %
  • toggle
  • 84.92 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.790s 174.005us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 56.721us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 30.143us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.480s 71.234us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 122.579us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 24.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 30.143us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 122.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.110s 298.331us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.250s 307.866us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.010s 21.093us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.630s 306.776us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.100s 332.277us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_prog_failure 2.630s 306.776us 1 1 100.00
lc_ctrl_errors 5.100s 332.277us 1 1 100.00
lc_ctrl_security_escalation 9.200s 470.207us 1 1 100.00
lc_ctrl_jtag_state_failure 47.640s 5016.352us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.560s 145.179us 1 1 100.00
lc_ctrl_jtag_errors 55.400s 5924.803us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.460s 2278.350us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.050s 1689.210us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.560s 145.179us 1 1 100.00
lc_ctrl_jtag_errors 55.400s 5924.803us 1 1 100.00
lc_ctrl_jtag_access 7.210s 1849.335us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.490s 1208.142us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.500s 131.095us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.160s 62.127us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.230s 3027.240us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.530s 8131.332us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.060s 68.435us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.350s 245.668us 1 1 100.00
lc_ctrl_jtag_alert_test 1.620s 217.434us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.930s 2260.055us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 20.993us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 105.510s 34719.074us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.310s 50.617us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 122.301us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 122.301us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 56.721us 1 1 100.00
lc_ctrl_csr_rw 0.920s 30.143us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 122.579us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.710s 90.252us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 56.721us 1 1 100.00
lc_ctrl_csr_rw 0.920s 30.143us 1 1 100.00
lc_ctrl_csr_aliasing 0.900s 122.579us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.710s 90.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 239.430us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 239.430us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.250s 307.866us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.770s 1201.791us 1 1 100.00
lc_ctrl_sec_cm 5.790s 120.645us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.200s 470.207us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.110s 298.331us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.050s 1689.210us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.780s 1254.201us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.780s 1254.201us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.010s 1437.729us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.510s 290.525us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.510s 290.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 39.430s 3529.170us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 113689872214411721177852292245939921080956783537949259923588376862328186547621 2291
UVM_INFO @ 3529169976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---