Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.23 %
  • code
  • 84.58 %
  • assert
  • 94.97 %
  • func
  • 94.13 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 79.27 %
  • toggle
  • 87.13 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.590s 403.941us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.260s 29.060us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 199.937us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.040s 219.958us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 20.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.200s 99.908us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 199.937us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 20.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.650s 110.632us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.590s 288.298us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 22.085us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.850s 316.854us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.040s 623.305us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_prog_failure 1.850s 316.854us 1 1 100.00
lc_ctrl_errors 7.040s 623.305us 1 1 100.00
lc_ctrl_security_escalation 7.350s 2040.710us 1 1 100.00
lc_ctrl_jtag_state_failure 27.530s 4978.335us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.280s 985.831us 1 1 100.00
lc_ctrl_jtag_errors 30.460s 14753.013us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.140s 990.137us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.850s 4381.915us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.280s 985.831us 1 1 100.00
lc_ctrl_jtag_errors 30.460s 14753.013us 1 1 100.00
lc_ctrl_jtag_access 15.440s 3338.376us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.870s 820.680us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.100s 172.842us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.530s 108.867us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.770s 1340.830us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.870s 1547.565us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.120s 17.066us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.800s 115.420us 1 1 100.00
lc_ctrl_jtag_alert_test 1.030s 213.091us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.730s 165.914us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.040s 12.837us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 183.440s 36383.428us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.870s 15.916us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 55.558us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 55.558us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.260s 29.060us 1 1 100.00
lc_ctrl_csr_rw 0.950s 199.937us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 20.119us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 231.563us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.260s 29.060us 1 1 100.00
lc_ctrl_csr_rw 0.950s 199.937us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 20.119us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 231.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
lc_ctrl_tl_intg_err 2.090s 369.804us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.090s 369.804us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.590s 288.298us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 12.100s 784.204us 1 1 100.00
lc_ctrl_sec_cm 5.650s 565.140us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.350s 2040.710us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.650s 110.632us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.850s 4381.915us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.280s 1518.629us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.280s 1518.629us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.680s 917.618us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.400s 795.802us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.400s 795.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 81.040s 7611.779us 1 1 100.00