Simulation Results: otp_ctrl

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.56 %
  • code
  • 79.15 %
  • assert
  • 94.18 %
  • func
  • 74.36 %
  • line
  • 88.79 %
  • branch
  • 84.58 %
  • cond
  • 92.93 %
  • toggle
  • 84.13 %
  • FSM
  • 45.31 %
Validation stages
V1
88.89%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.960s 808.215us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.950s 276.618us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.460s 111.292us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.620s 878.634us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 115.949us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.030s 430.189us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.460s 111.292us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 115.949us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.170s 42.611us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.750s 42.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.130s 1618.053us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.940s 395.904us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 24.230s 13022.996us 1 1 100.00
otp_ctrl_check_fail 10.940s 1259.322us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.510s 777.530us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 3.410s 695.188us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 22.810s 1834.832us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 6.890s 230.096us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 20.210s 987.794us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 10.090s 1265.248us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 32.500s 5664.974us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.680s 88.583us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.580s 75.475us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.890s 240.957us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.890s 240.957us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.950s 276.618us 1 1 100.00
otp_ctrl_csr_rw 1.460s 111.292us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 115.949us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.920s 284.817us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.950s 276.618us 1 1 100.00
otp_ctrl_csr_rw 1.460s 111.292us 1 1 100.00
otp_ctrl_csr_aliasing 2.630s 115.949us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.920s 284.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
otp_ctrl_tl_intg_err 29.760s 19107.247us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 29.760s 19107.247us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_macro_errs 20.210s 987.794us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_macro_errs 20.210s 987.794us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.880s 1577.321us 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.940s 395.904us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 10.940s 1259.322us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.100s 352.211us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 125.240s 42055.751us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.510s 777.530us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 12.450s 2197.166us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 20.210s 987.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.440s 3649.234us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 46.550s 1992.303us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 19955316481387233229843426119719294328475894762921190465526757731880345965655 92
UVM_INFO @ 430189442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---