Simulation Results: pwrmgr

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 92.87 %
  • assert
  • 98.69 %
  • func
  • 98.35 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.47 %
  • toggle
  • 99.62 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 31.164us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.840s 32.112us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.740s 1493.980us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.280s 25.314us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.830s 59.057us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 25.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.810s 48.334us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.810s 48.334us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.000s 66.309us 1 1 100.00
pwrmgr_lowpower_invalid 0.650s 55.705us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.320s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.770s 78.348us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.320s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.620s 72.662us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.800s 125.144us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.040s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.020s 1951.851us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.720s 21.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.040s 97.052us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.040s 97.052us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.840s 32.112us 1 1 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 25.314us 1 1 100.00
pwrmgr_same_csr_outstanding 0.850s 152.372us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.840s 32.112us 1 1 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 25.314us 1 1 100.00
pwrmgr_same_csr_outstanding 0.850s 152.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.970s 147.901us 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.970s 147.901us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.380s 1000.065us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.620s 72.662us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.550s 1188.021us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.830s 72.472us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 41.162us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.070s 328.824us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 59.415us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.570s 38.074us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.640s 102.211us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.760s 29.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.670s 102.706us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.200s 2555.984us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_reset 43575374630158711592423015642993974880559229384341637019127899100123750761112 109
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 48898623135524198625398115171825268904292157651455527064746410744117835560190 143
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 31184910254747728380682112838884527487206141164753254521083106432659046074641 79
UVM_ERROR @ 102706352 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102706352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst 1 test run
pwrmgr_reset_invalid 111208683509355715998869803836154508233141734172428524152189913941008710455192 109
UVM_INFO @ 78347985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---