Simulation Results: rom_ctrl/32kb

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 97.11 %
  • assert
  • 96.95 %
  • func
  • 96.18 %
  • line
  • 99.33 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 95.57 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.590s 141.238us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.550s 786.725us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.120s 209.957us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.350s 206.486us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 556.675us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.390s 324.286us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.120s 209.957us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 556.675us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.490s 127.010us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.600s 188.540us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.910s 520.093us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.620s 622.311us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.840s 3370.532us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.010s 676.740us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.690s 614.347us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.690s 614.347us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.550s 786.725us 1 1 100.00
rom_ctrl_csr_rw 3.120s 209.957us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 556.675us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.400s 166.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.550s 786.725us 1 1 100.00
rom_ctrl_csr_rw 3.120s 209.957us 1 1 100.00
rom_ctrl_csr_aliasing 3.540s 556.675us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.400s 166.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.990s 2312.086us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
rom_ctrl_tl_intg_err 23.920s 1450.023us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.590s 141.238us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.590s 141.238us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.590s 141.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.920s 1450.023us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
rom_ctrl_kmac_err_chk 5.840s 3370.532us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.550s 6222.372us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.990s 2312.086us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.010s 1778.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 93.630s 10294.575us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 86422928202059395587602439875287516066853670952453127144355122095310563352744 79
UVM_INFO @ 520093059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---