Simulation Results: rom_ctrl/64kb

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.58 %
  • code
  • 98.55 %
  • assert
  • 97.53 %
  • func
  • 96.66 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.07 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.840s 762.226us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.700s 1035.535us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.683us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.510s 295.065us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 423.099us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.120s 986.668us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.900s 212.683us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 423.099us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.370s 554.755us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.960s 1028.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.920s 795.580us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.210s 778.571us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.510s 875.174us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.250s 453.330us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.020s 288.234us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.020s 288.234us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.700s 1035.535us 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.683us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 423.099us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.760s 215.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.700s 1035.535us 1 1 100.00
rom_ctrl_csr_rw 5.900s 212.683us 1 1 100.00
rom_ctrl_csr_aliasing 5.800s 423.099us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.760s 215.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.760s 3149.298us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
rom_ctrl_tl_intg_err 99.510s 1535.723us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.840s 762.226us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.840s 762.226us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.840s 762.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 99.510s 1535.723us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
rom_ctrl_kmac_err_chk 12.510s 875.174us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 160.880s 4228.891us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.760s 3149.298us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 452.650s 780.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 58.880s 2336.659us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 64741002810450207048227679184193916685357887007732902188005702202630708767737 79
UVM_INFO @ 795580359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---