Simulation Results: rstmgr

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.95 %
  • code
  • 99.41 %
  • assert
  • 98.66 %
  • func
  • 95.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.450s 140.820us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.880s 106.067us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.580s 1471.877us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.760s 154.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.280s 209.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00
rstmgr_csr_aliasing 1.760s 154.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.830s 159.707us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.230s 485.913us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.220s 189.989us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.130s 1582.965us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.130s 1582.965us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.130s 1582.965us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.130s 1582.965us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 14.180s 6153.572us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 71.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.920s 169.990us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.920s 169.990us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.880s 106.067us 1 1 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00
rstmgr_csr_aliasing 1.760s 154.613us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 131.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.880s 106.067us 1 1 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00
rstmgr_csr_aliasing 1.760s 154.613us 1 1 100.00
rstmgr_same_csr_outstanding 1.090s 131.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.390s 8463.094us 1 1 100.00
rstmgr_tl_intg_err 2.510s 950.797us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.390s 8463.094us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.390s 8463.094us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.510s 950.797us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.050s 204.490us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.790s 2808.764us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.540s 301.872us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.390s 8463.094us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.730s 70.697us 1 1 100.00