Simulation Results: rstmgr_cnsty_chk

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rstmgr_cnsty_chk_test 1.900s 8637.082us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 48345038897084169818759107928503081580443989117802362476889447165401435212195 175
UVM_INFO @ 1768221579 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1785821579 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1803421579 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1821021579 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
Job cancelled because all of its dependencies failed or were killed. 1 test run
rstmgr_cnsty_chk None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
rstmgr_cnsty_chk None None