Simulation Results: rv_timer

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.02 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 90.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.780s 178.016us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 42.558us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 17.666us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.290s 311.677us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.750s 213.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.880s 66.238us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 17.666us 1 1 100.00
rv_timer_csr_aliasing 0.750s 213.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.800s 557.498us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.400s 2271.304us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 146.980s 481107.105us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 146.980s 481107.105us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.290s 2369.467us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 24.833us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.710s 13.796us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.030s 89.979us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.030s 89.979us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 42.558us 1 1 100.00
rv_timer_csr_rw 0.590s 17.666us 1 1 100.00
rv_timer_csr_aliasing 0.750s 213.386us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 214.172us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 42.558us 1 1 100.00
rv_timer_csr_rw 0.590s 17.666us 1 1 100.00
rv_timer_csr_aliasing 0.750s 213.386us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 214.172us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 46.621us 1 1 100.00
rv_timer_tl_intg_err 0.850s 41.380us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.850s 41.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.990s 206.138us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.600s 42.588us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.950s 8058.260us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 15342838239692980987545609424315391990774342663985949918929840044271833319997 78
UVM_INFO @ 206138212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 93981505816191094851013158422408536796110402116158316533638132119451024072392 78
UVM_INFO @ 557497693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 22456197717433332992280781017542839791339356535491462146236382745577751452617 75
UVM_INFO @ 42587760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---