Simulation Results: spi_host

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 87.39 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 23.000s 1061.635us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.489us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 16.722us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1389.254us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 40.953us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 20.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 16.722us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.953us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 30.199us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 19.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 24.832us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 18.000s 3483.292us 1 1 100.00
spi_host_error_cmd 1.000s 24.372us 1 1 100.00
spi_host_event 21.000s 4121.389us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 83.498us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 83.498us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 83.498us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 178.000s 7236.428us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 52.000s 4029.457us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 135.598us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 83.498us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 83.498us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 23.000s 1061.635us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 23.000s 1061.635us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 6.000s 725.229us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 1412.747us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 53.000s 5479.959us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 33.824us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 18.000s 3483.292us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 46.993us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 42.465us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 1459.359us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 1459.359us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.489us 1 1 100.00
spi_host_csr_rw 1.000s 16.722us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.953us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 102.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.489us 1 1 100.00
spi_host_csr_rw 1.000s 16.722us 1 1 100.00
spi_host_csr_aliasing 1.000s 40.953us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 102.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 89.784us 1 1 100.00
spi_host_sec_cm 1.000s 49.091us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 89.784us 1 1 100.00