Simulation Results: sram_ctrl/main

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.29 %
  • code
  • 95.69 %
  • assert
  • 97.82 %
  • func
  • 92.35 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 710.160us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 38.366us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 32.611us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 204.997us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 31.578us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 2014.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 32.611us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 31.578us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 93.000s 3085.010us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 98.000s 5594.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 32.000s 79561.095us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 163.000s 5379.836us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 157.000s 15145.133us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 16697.799us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 27.000s 33984.094us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 29.000s 26603.569us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 378.397us 1 1 100.00
sram_ctrl_partial_access_b2b 140.000s 13800.084us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 3299.462us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 666.339us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 6640.379us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4185.546us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 356.300us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 83.000s 110592.255us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 16.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 101.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 101.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 38.366us 1 1 100.00
sram_ctrl_csr_rw 2.000s 32.611us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 31.578us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 38.366us 1 1 100.00
sram_ctrl_csr_rw 2.000s 32.611us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 31.578us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 28223.215us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 659.394us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 659.394us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4185.546us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4185.546us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 32.611us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 29.000s 26603.569us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 26603.569us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 26603.569us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 27.000s 33984.094us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 8275.443us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 28223.215us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 2775.831us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 710.160us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 710.160us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 29.000s 26603.569us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 27.000s 33984.094us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 710.160us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 386.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 36.000s 3556.405us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 13662275961487328175778266580934420823839561904547741218099895706812063203655 86
UVM_INFO @ 3299462256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 112848156311301544308156866919126879896382275214970318225179035715812177238104 86
UVM_INFO @ 666338722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 30667145437839862633898130023087251507932381442115112781232119772499774095323 86
UVM_INFO @ 6640378826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---