Simulation Results: sram_ctrl/ret

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.06 %
  • code
  • 83.33 %
  • assert
  • 97.67 %
  • func
  • 95.20 %
  • block
  • 93.76 %
  • line
  • 94.99 %
  • branch
  • 89.36 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 140.489us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 13.035us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.503us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 124.185us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.822us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 144.648us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.503us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.822us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 6389.793us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 42.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 384.044us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 147.000s 6204.446us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 517.640us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 502.651us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1001.076us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 669.182us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 533.445us 1 1 100.00
sram_ctrl_partial_access_b2b 179.000s 53108.851us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 104.436us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 99.580us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 35.339us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 7214.685us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.252us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 31.000s 12960.413us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 23.339us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 32.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 32.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.035us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.503us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.822us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.025us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.035us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.503us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.822us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 285.999us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 717.178us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 717.178us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 7214.685us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 7214.685us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.503us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 669.182us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 669.182us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 669.182us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1001.076us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 54.253us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 285.999us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 702.443us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 140.489us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 140.489us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 669.182us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1001.076us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 140.489us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1420.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 29.000s 6035.920us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 93628156226153430520149061037180703216905157757941058922986667848532348854184 86
UVM_INFO @ 104436131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 63598922854178462636418325474701892823435811774858649038236753805008591854308 86
UVM_INFO @ 99579639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 67355103754584535267808405999372208063120459208758193789462671952164814210461 86
UVM_INFO @ 35338874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---