Simulation Results: sysrst_ctrl

 
22/06/2026 15:30:25 DVSim: v1.49.10 sha: c4c7114 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.65 %
  • code
  • 93.35 %
  • assert
  • 95.50 %
  • func
  • 65.11 %
  • line
  • 97.86 %
  • branch
  • 97.78 %
  • cond
  • 95.18 %
  • toggle
  • 99.66 %
  • FSM
  • 76.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.920s 2119.892us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.890s 2459.367us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.600s 2188.774us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.270s 2367.546us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 6.130s 6052.084us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.150s 2027.312us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 17.700s 39177.318us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2460.392us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.540s 2081.927us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.150s 2027.312us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2460.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 26.270s 58342.030us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 35.730s 117094.904us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 42.620s 98793.017us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.110s 2991.085us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.960s 2510.171us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.960s 2196.690us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.030s 3475.385us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.100s 2609.307us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.120s 5875.134us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 6.760s 41702.380us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 7.690s 8878.495us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.980s 2084.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.530s 2046.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.120s 2227.108us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.120s 2227.108us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.130s 6052.084us 1 1 100.00
sysrst_ctrl_csr_rw 4.150s 2027.312us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2460.392us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.480s 7086.355us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.130s 6052.084us 1 1 100.00
sysrst_ctrl_csr_rw 4.150s 2027.312us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.890s 2460.392us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.480s 7086.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 66.570s 42009.085us 1 1 100.00
sysrst_ctrl_tl_intg_err 15.770s 43650.399us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 15.770s 43650.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.940s 7890.590us 1 1 100.00