Simulation Results

Simulation Results: adc_ctrl

23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.64 %

code
92.13 %

assert
91.90 %

func
12.89 %

line
98.00 %

branch
96.29 %

cond
86.23 %

toggle
99.05 %

FSM
81.08 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	2.800s	5889.769us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	0.740s	634.310us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.750s	426.166us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	3.250s	1145.184us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.150s	1374.131us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.520s	580.645us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.750s	426.166us	1	1	100.00
	adc_ctrl_csr_aliasing	2.150s	1374.131us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	1.020s	305.232us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	0.790s	514.258us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	1.290s	506.130us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.770s	356.814us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.740s	369.916us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.650s	476.605us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	0.720s	361.823us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	1.130s	431.798us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	2.720s	3130.115us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	20.900s	30059.514us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	41.760s	81044.814us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	6.400s	11660.939us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.650s	305.673us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.740s	374.191us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.950s	761.964us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.950s	761.964us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.740s	634.310us	1	1	100.00
	adc_ctrl_csr_rw	0.750s	426.166us	1	1	100.00
	adc_ctrl_csr_aliasing	2.150s	1374.131us	1	1	100.00
	adc_ctrl_same_csr_outstanding	1.690s	2341.711us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.740s	634.310us	1	1	100.00
	adc_ctrl_csr_rw	0.750s	426.166us	1	1	100.00
	adc_ctrl_csr_aliasing	2.150s	1374.131us	1	1	100.00
	adc_ctrl_same_csr_outstanding	1.690s	2341.711us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	11.620s	7833.582us	1	1	100.00
	adc_ctrl_tl_intg_err	7.750s	8648.195us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	7.750s	8648.195us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	adc_ctrl_stress_all_with_rand_reset	1.690s	864.147us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	7342839705904575927208396682641006000810820623987482419667401489407948952321	386	UVM_INFO @ 305231743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	52086785374683876044333257476749101423474724617312106601867395801754251223000	386	UVM_INFO @ 514257810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	87883354935603804481191105348582267167583982934252529171431289623261159270421	386	UVM_INFO @ 506129797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	82159701052372437249316383724871173179007500658926384742046957139470778708113	386	UVM_INFO @ 356814411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	36823696749876216558907327250737798452913934217053695029047923671520798959042	386	UVM_INFO @ 369916250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	95548520464624921410201539955862353091676139828984110518172978993517605369881	386	UVM_INFO @ 476604587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	47386859112771371813294705365253967496511015890829168884691454239212843098206	386	UVM_INFO @ 431798367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	74445394724649136559650317364623592474311543931953593464169117082972156405839	386	UVM_INFO @ 361822763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	19825055706775305638310232061511337894850941385255257389376136398662989095751	392	UVM_INFO @ 864146569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---