Simulation Results: aes/masked

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.08 %
  • code
  • 93.69 %
  • assert
  • 98.23 %
  • func
  • 75.33 %
  • block
  • 94.34 %
  • line
  • 96.07 %
  • branch
  • 87.37 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 332.151us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 113.448us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 150.661us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 84.983us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1057.912us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 132.968us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 66.644us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 84.983us 1 1 100.00
aes_csr_aliasing 2.000s 132.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 113.448us 1 1 100.00
aes_config_error 3.000s 455.009us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 113.448us 1 1 100.00
aes_config_error 3.000s 455.009us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_b2b 8.000s 560.911us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 113.448us 1 1 100.00
aes_config_error 3.000s 455.009us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 100.013us 1 1 100.00
aes_config_error 3.000s 455.009us 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 116.230us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 363.651us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_sideload 6.000s 182.716us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 231.454us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 397.277us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 57.107us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 73.597us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 73.597us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 150.661us 1 1 100.00
aes_csr_rw 2.000s 84.983us 1 1 100.00
aes_csr_aliasing 2.000s 132.968us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.805us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 150.661us 1 1 100.00
aes_csr_rw 2.000s 84.983us 1 1 100.00
aes_csr_aliasing 2.000s 132.968us 1 1 100.00
aes_same_csr_outstanding 2.000s 66.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 1102.193us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 131.564us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 2479.800us 1 1 100.00
aes_tl_intg_err 1.000s 244.431us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 244.431us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 113.448us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
aes_core_fi 4.000s 749.279us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 455.009us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_core_fi 4.000s 749.279us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.791us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 347.522us 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 188.893us 1 1 100.00
aes_sideload 6.000s 182.716us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 347.522us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 347.522us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 347.522us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 347.522us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 347.522us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 188.893us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 483.840us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 483.840us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 483.840us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 483.840us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 83.222us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_ctr_fi 3.000s 60.325us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 483.840us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 483.840us 0 1 0.00
aes_control_fi 2.000s 64.925us 1 1 100.00
aes_cipher_fi 3.000s 62.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 6.000s 2049.492us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 47833025975012785129478906838236067976331240935043640083663221368278540412823 10937
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 37827741381522203978965635592184116797557917248824959768397554891368645433250 101698
TEST FAILED MESSAGES DID NOT MATCH
0 a9 dc dc 0
1 00 3a 3a 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 96586985207387823240459990614145898106891386937576604242014321996351923080725 203
UVM_INFO @ 2049491599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---