Simulation Results: aes/unmasked

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 89.73 %
  • assert
  • 97.73 %
  • func
  • 74.57 %
  • block
  • 89.65 %
  • line
  • 92.00 %
  • branch
  • 80.06 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 67.947us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 123.568us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 64.384us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 107.029us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 4276.565us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 311.029us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 70.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 107.029us 1 1 100.00
aes_csr_aliasing 3.000s 311.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 123.568us 1 1 100.00
aes_config_error 3.000s 115.801us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 123.568us 1 1 100.00
aes_config_error 3.000s 115.801us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_b2b 2.000s 174.240us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 123.568us 1 1 100.00
aes_config_error 3.000s 115.801us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 118.055us 1 1 100.00
aes_config_error 3.000s 115.801us 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 197.929us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 490.760us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_sideload 3.000s 148.645us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 344.224us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10.000s 43.412us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 59.558us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 64.066us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 64.066us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.384us 1 1 100.00
aes_csr_rw 2.000s 107.029us 1 1 100.00
aes_csr_aliasing 3.000s 311.029us 1 1 100.00
aes_same_csr_outstanding 1.000s 109.620us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 64.384us 1 1 100.00
aes_csr_rw 2.000s 107.029us 1 1 100.00
aes_csr_aliasing 3.000s 311.029us 1 1 100.00
aes_same_csr_outstanding 1.000s 109.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 151.387us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 1121.163us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1001.230us 1 1 100.00
aes_tl_intg_err 3.000s 132.836us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 132.836us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 123.568us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
aes_core_fi 2.000s 67.653us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 115.801us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_core_fi 2.000s 67.653us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 69.543us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 57.804us 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 71.282us 1 1 100.00
aes_sideload 3.000s 148.645us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.804us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.804us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 57.804us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 57.804us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 57.804us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 71.282us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.512us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.512us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.512us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.512us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 7.000s 648.485us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_ctr_fi 2.000s 56.460us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 173.512us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 173.512us 0 1 0.00
aes_control_fi 1.000s 54.209us 1 1 100.00
aes_cipher_fi 2.000s 61.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 2455.533us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 61031666151434689987474337367270642843371630676810842045834446542144328746036 6010
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 11020407989350055944251209711069570744067561706230026785977732949108290089154 7775
UVM_INFO @ 43412480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 100803505419919945502899808736063956283781918308453778684535216286537608786946 394
UVM_INFO @ 2455533160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---