Simulation Results: chip

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.41 %
  • code
  • 84.56 %
  • assert
  • 97.49 %
  • func
  • 44.18 %
  • line
  • 94.25 %
  • branch
  • 93.66 %
  • cond
  • 89.22 %
  • toggle
  • 88.51 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.34%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 173.080s 3234.501us 1 1 100.00
chip_sw_example_rom 78.880s 2404.458us 1 1 100.00
chip_sw_example_manufacturer 170.780s 2493.317us 1 1 100.00
chip_sw_example_concurrency 214.050s 2804.697us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 320.030s 5961.538us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 213.130s 4165.346us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 751.590s 8865.278us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4915.120s 33303.529us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 51.200s 2109.854us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4915.120s 33303.529us 1 1 100.00
chip_csr_rw 213.130s 4165.346us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.510s 44.395us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 361.660s 4445.462us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 361.660s 4445.462us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 361.660s 4445.462us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 385.930s 4469.764us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 385.930s 4469.764us 1 1 100.00
chip_sw_uart_tx_rx_idx1 419.670s 3974.810us 1 1 100.00
chip_sw_uart_tx_rx_idx2 417.970s 4843.817us 1 1 100.00
chip_sw_uart_tx_rx_idx3 354.320s 4985.888us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1002.130s 8782.905us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 432.000s 4674.448us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 289.310s 4174.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 214.780s 4720.292us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 214.780s 4720.292us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 161.880s 3414.405us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 176.960s 3130.045us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 197.370s 3828.398us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 737.760s 11003.649us 1 1 100.00
chip_tap_straps_testunlock0 181.260s 3908.664us 1 1 100.00
chip_tap_straps_rma 444.780s 7174.982us 1 1 100.00
chip_tap_straps_prod 1117.480s 16063.372us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 796.890s 8993.617us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 551.740s 6426.790us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 551.740s 6426.790us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 687.510s 8211.848us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1184.940s 11975.918us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 388.000s 4470.018us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 654.940s 5637.721us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3948.720s 19653.544us 1 1 100.00
chip_sw_aes_enc_jitter_en 241.250s 3944.658us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 876.010s 6715.408us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.410s 3137.324us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1788.850s 13499.347us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 231.560s 3704.693us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 366.010s 4924.841us 1 1 100.00
chip_sw_clkmgr_jitter 196.330s 3013.735us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 242.290s 4034.260us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 413.240s 5454.170us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 277.360s 5606.395us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 192.270s 3282.284us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 277.360s 5606.395us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 148.540s 3113.677us 1 1 100.00
chip_sw_aes_smoketest 153.810s 3058.870us 1 1 100.00
chip_sw_aon_timer_smoketest 217.280s 2666.070us 1 1 100.00
chip_sw_clkmgr_smoketest 119.490s 2557.304us 1 1 100.00
chip_sw_csrng_smoketest 192.760s 3446.475us 1 1 100.00
chip_sw_entropy_src_smoketest 975.050s 7125.840us 1 1 100.00
chip_sw_gpio_smoketest 211.330s 3724.832us 1 1 100.00
chip_sw_hmac_smoketest 176.930s 3246.286us 1 1 100.00
chip_sw_kmac_smoketest 244.640s 3739.826us 1 1 100.00
chip_sw_otbn_smoketest 1013.820s 7650.391us 1 1 100.00
chip_sw_pwrmgr_smoketest 338.060s 6374.430us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 266.630s 5431.973us 1 1 100.00
chip_sw_rv_plic_smoketest 165.070s 2841.630us 1 1 100.00
chip_sw_rv_timer_smoketest 181.140s 2974.608us 1 1 100.00
chip_sw_rstmgr_smoketest 136.400s 3311.692us 1 1 100.00
chip_sw_sram_ctrl_smoketest 141.540s 2583.322us 1 1 100.00
chip_sw_uart_smoketest 169.650s 2987.611us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 162.790s 2935.603us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 308.230s 4080.966us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8547.030s 63260.343us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3213.770s 16088.852us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 189.513s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 215.240s 2711.280us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 157.900s 3811.208us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7374.540s 55185.498us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7623.180s 58121.690us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 45.610s 2185.892us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 45.610s 2185.892us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4915.120s 33303.529us 1 1 100.00
chip_same_csr_outstanding 3013.400s 30660.316us 1 1 100.00
chip_csr_hw_reset 320.030s 5961.538us 1 1 100.00
chip_csr_rw 213.130s 4165.346us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4915.120s 33303.529us 1 1 100.00
chip_same_csr_outstanding 3013.400s 30660.316us 1 1 100.00
chip_csr_hw_reset 320.030s 5961.538us 1 1 100.00
chip_csr_rw 213.130s 4165.346us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 6.190s 62.958us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.550s 53.241us 1 1 100.00
xbar_smoke_large_delays 43.270s 6375.995us 1 1 100.00
xbar_smoke_slow_rsp 42.720s 4585.413us 1 1 100.00
xbar_random_zero_delays 11.880s 181.636us 1 1 100.00
xbar_random_large_delays 310.370s 53428.622us 1 1 100.00
xbar_random_slow_rsp 211.500s 25322.619us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.350s 423.766us 1 1 100.00
xbar_error_and_unmapped_addr 26.990s 1085.877us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 25.560s 1153.346us 1 1 100.00
xbar_error_and_unmapped_addr 26.990s 1085.877us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 63.210s 2613.559us 1 1 100.00
xbar_access_same_device_slow_rsp 559.410s 66036.214us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 22.570s 1065.079us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 177.360s 3029.617us 1 1 100.00
xbar_stress_all_with_error 18.250s 640.795us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 300.240s 5594.053us 1 1 100.00
xbar_stress_all_with_reset_error 182.060s 1815.150us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3213.770s 16088.852us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2621.990s 26362.470us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3055.830s 14354.334us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 29.938s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 21.612s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 13.247s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 16.806s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 33.833s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 38.862s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 32.431s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 34.907s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 15.458s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 33.634s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 116.419s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 51.150s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 68.153s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 49.641s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 31.915s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20.210s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 24.280s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.830s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.140s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.090s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.920s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.030s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.070s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.880s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.670s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.320s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.950s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.420s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 21.350s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.710s 10.180us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 41.280s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 79.808s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 62.481s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 53.835s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 46.978s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 3347.600s 17813.188us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 6031.310s 29098.459us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6190.230s 28483.878us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3314.810s 16047.696us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3186.910s 34636.604us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3186.910s 34636.604us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 179.650s 3208.797us 1 1 100.00
chip_sw_aes_enc_jitter_en 241.250s 3944.658us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 124.370s 2353.493us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 149.210s 2515.299us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1294.300s 11107.192us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 193.540s 3231.901us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 359.150s 5943.453us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 581.760s 5244.279us 1 1 100.00
chip_plic_all_irqs_10 339.880s 3709.012us 1 1 100.00
chip_plic_all_irqs_20 450.550s 4700.190us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 237.930s 3330.368us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1202.680s 12948.433us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 327.940s 4477.158us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 115.230s 2771.638us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.166s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 867.820s 6986.424us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1006.360s 7680.969us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 858.230s 8158.049us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9269.240s 256549.700us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 236.230s 3525.850us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 338.060s 6374.430us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 236.230s 3525.850us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 359.870s 7433.768us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 359.870s 7433.768us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 389.360s 6908.928us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 490.010s 6380.992us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 593.480s 6310.481us 1 1 100.00
chip_sw_aes_idle 149.210s 2515.299us 1 1 100.00
chip_sw_hmac_enc_idle 190.900s 3223.262us 1 1 100.00
chip_sw_kmac_idle 161.160s 2688.202us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 275.190s 4055.179us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 310.420s 3861.326us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 373.020s 4718.297us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 313.980s 4138.608us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 854.400s 9206.397us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 424.910s 4136.967us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 431.800s 4983.316us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 451.650s 4569.039us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 416.770s 4533.429us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 383.590s 3869.937us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 451.560s 5117.425us 1 1 100.00
chip_sw_ast_clk_outputs 687.510s 8211.848us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 552.560s 11439.631us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 451.650s 4569.039us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 416.770s 4533.429us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 388.000s 4470.018us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 654.940s 5637.721us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3948.720s 19653.544us 1 1 100.00
chip_sw_aes_enc_jitter_en 241.250s 3944.658us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 876.010s 6715.408us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.410s 3137.324us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1788.850s 13499.347us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 231.560s 3704.693us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 366.010s 4924.841us 1 1 100.00
chip_sw_clkmgr_jitter 196.330s 3013.735us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 196.250s 3295.990us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 387.030s 4986.843us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 719.510s 7471.832us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4306.830s 25394.680us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 162.290s 2917.539us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 200.330s 3644.381us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 862.370s 9726.261us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 179.250s 3249.224us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 342.900s 5460.784us 1 1 100.00
chip_sw_flash_init_reduced_freq 1131.610s 25039.323us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2453.400s 19147.514us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 687.510s 8211.848us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 425.590s 4615.507us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 291.330s 3794.734us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 867.820s 6986.424us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2298.340s 24081.388us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 173.470s 3464.974us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 525.870s 7942.822us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 216.590s 3131.928us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2245.910s 14604.300us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 135.440s 2943.199us 1 1 100.00
chip_sw_edn_entropy_reqs 762.950s 7145.640us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 135.440s 2943.199us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2298.340s 24081.388us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 156.850s 2601.264us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1395.200s 19439.020us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 578.210s 6141.809us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 654.940s 5637.721us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 382.330s 4162.775us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 388.000s 4470.018us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3646.440s 44430.253us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1395.200s 19439.020us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 261.420s 3395.971us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3646.440s 44430.253us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 271.670s 8355.038us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 614.290s 5351.496us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 373.060s 5207.843us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 373.060s 5207.843us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 180.270s 3232.830us 1 1 100.00
chip_sw_hmac_enc_jitter_en 178.410s 3137.324us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 190.900s 3223.262us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1348.620s 10446.151us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1836.620s 12026.757us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 468.450s 4870.485us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 396.250s 4476.794us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 536.040s 5738.729us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 330.000s 4500.351us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1788.850s 13499.347us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1766.580s 12831.342us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1294.300s 11107.192us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4755.280s 20018.653us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 204.870s 3332.788us 1 1 100.00
chip_sw_kmac_mode_kmac 207.580s 3862.913us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 231.560s 3704.693us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 184.940s 3614.316us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 579.890s 4861.385us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 161.160s 2688.202us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 359.150s 5943.453us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 737.760s 11003.649us 1 1 100.00
chip_tap_straps_rma 444.780s 7174.982us 1 1 100.00
chip_tap_straps_prod 1117.480s 16063.372us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 148.910s 2973.774us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1882.880s 13652.854us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_sw_flash_ctrl_lc_rw_en 154.340s 3239.541us 0 1 0.00
chip_sw_flash_rma_unlocked 3646.440s 44430.253us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.260s 2654.691us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 623.790s 7977.197us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 499.630s 5576.195us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 458.190s 6382.346us 0 1 0.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.020s 10260.578us 1 1 100.00
chip_sw_sram_ctrl_execution_main 575.590s 9702.503us 1 1 100.00
chip_prim_tl_access 271.670s 8355.038us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 552.560s 11439.631us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 424.910s 4136.967us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 431.800s 4983.316us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 451.650s 4569.039us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 416.770s 4533.429us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 383.590s 3869.937us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 451.560s 5117.425us 1 1 100.00
chip_tap_straps_dev 737.760s 11003.649us 1 1 100.00
chip_tap_straps_rma 444.780s 7174.982us 1 1 100.00
chip_tap_straps_prod 1117.480s 16063.372us 1 1 100.00
chip_rv_dm_lc_disabled 492.000s 15898.258us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 146.330s 3176.242us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 82.400s 3829.237us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 93.860s 3130.217us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 84.270s 3425.957us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_sw_lc_walkthrough_testunlocks 1426.550s 26903.160us 1 1 100.00
chip_rv_dm_lc_disabled 492.000s 15898.258us 1 1 100.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 671.540s 9791.700us 0 1 0.00
chip_sw_lc_walkthrough_prod 684.110s 10621.786us 0 1 0.00
chip_sw_lc_walkthrough_prodend 739.830s 26501.723us 0 1 0.00
chip_sw_lc_walkthrough_rma 372.700s 5611.357us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1426.550s 26903.160us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 77.320s 2320.275us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 58.980s 2420.967us 1 1 100.00
rom_volatile_raw_unlock 21.095s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4022.250s 17860.456us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3948.720s 19653.544us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 593.480s 6310.481us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 593.480s 6310.481us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 593.480s 6310.481us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 336.630s 3657.597us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1395.200s 19439.020us 1 1 100.00
chip_sw_otbn_mem_scramble 336.630s 3657.597us 1 1 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 477.910s 6425.113us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.820s 3436.727us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1395.200s 19439.020us 1 1 100.00
chip_sw_otbn_mem_scramble 336.630s 3657.597us 1 1 100.00
chip_sw_keymgr_key_derivation 689.320s 6567.709us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 477.910s 6425.113us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.820s 3436.727us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 348.110s 5511.140us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 148.910s 2973.774us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.260s 2654.691us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 623.790s 7977.197us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 499.630s 5576.195us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 458.190s 6382.346us 0 1 0.00
chip_sw_lc_ctrl_transition 795.070s 11085.624us 1 1 100.00
chip_prim_tl_access 271.670s 8355.038us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 271.670s 8355.038us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 848.440s 8068.715us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.180s 2601.914us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1117.950s 24724.608us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 207.660s 6665.951us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 501.770s 8892.918us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 360.440s 6446.865us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 947.630s 25848.386us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 950.300s 13172.018us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 359.870s 7433.768us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 807.030s 9234.948us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 306.260s 5422.678us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.180s 2601.914us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 241.290s 4768.938us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2430.910s 31281.180us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 310.730s 6364.981us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 162.600s 2846.037us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 640.760s 11753.363us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 537.610s 8514.916us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 879.160s 10181.775us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1991.540s 28945.452us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 184.530s 2898.842us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.020s 10260.578us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 336.020s 10260.578us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 879.160s 10181.775us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 640.760s 11753.363us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 306.260s 5422.678us 1 1 100.00
chip_sw_pwrmgr_smoketest 338.060s 6374.430us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 285.130s 3961.126us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 490.240s 7976.934us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 278.960s 3761.815us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1202.680s 12948.433us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 189.290s 3459.947us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1006.360s 7680.969us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 476.530s 4687.782us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 522.850s 4521.113us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 205.060s 3190.438us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.820s 3436.727us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 490.240s 7976.934us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 490.240s 7976.934us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 113.670s 2926.780us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 694.540s 10628.566us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 885.560s 13796.052us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 285.130s 3961.126us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 199.140s 3781.884us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 313.060s 6170.010us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 444.780s 7174.982us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 492.000s 15898.258us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 581.760s 5244.279us 1 1 100.00
chip_plic_all_irqs_10 339.880s 3709.012us 1 1 100.00
chip_plic_all_irqs_20 450.550s 4700.190us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 177.360s 3123.580us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 170.170s 2986.454us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3213.770s 16088.852us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 222.360s 4138.633us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 227.540s 3693.194us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 199.840s 3663.821us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 184.590s 2611.420us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 477.910s 6425.113us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 366.010s 4924.841us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 535.730s 8071.760us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 448.480s 9125.202us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 575.590s 9702.503us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
chip_sw_data_integrity_escalation 551.740s 6426.790us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 537.610s 8514.916us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1152.030s 22763.802us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 176.380s 2446.250us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 218.830s 3793.186us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 324.090s 3947.188us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1152.030s 22763.802us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1152.030s 22763.802us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2441.530s 20330.025us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2441.530s 20330.025us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 336.930s 6177.548us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3186.910s 34636.604us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 119.780s 3049.774us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 159.730s 3195.028us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 349.230s 4636.123us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 355.420s 3781.844us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 969.770s 8282.958us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5374.940s 31763.049us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1891.580s 12455.861us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 148.120s 2607.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 221.670s 3085.634us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 121.000s 2658.275us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10410.180s 72096.240us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1124.830s 6909.646us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 180.540s 4726.302us 0 1 0.00
rom_e2e_jtag_debug_dev 191.180s 4823.763us 0 1 0.00
rom_e2e_jtag_debug_rma 458.630s 7672.281us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 271.340s 5435.941us 0 1 0.00
rom_e2e_jtag_inject_dev 68.030s 2133.811us 0 1 0.00
rom_e2e_jtag_inject_rma 70.720s 2092.203us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 36.796s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 294.110s 4388.943us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 324.140s 2615.816us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 510.920s 4420.307us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 990.510s 7271.242us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 241.220s 2827.740us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 648.100s 5132.272us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 82.730s 1978.657us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 198.560s 2671.163us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 285.500s 6083.264us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 259.770s 4785.490us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 879.160s 10181.775us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 180.540s 4726.302us 0 1 0.00
rom_e2e_jtag_debug_dev 191.180s 4823.763us 0 1 0.00
rom_e2e_jtag_debug_rma 458.630s 7672.281us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 386.440s 4823.876us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 500.400s 6532.753us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5670.710s 38907.466us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5670.710s 38907.466us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 221.160s 3817.284us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 385.930s 4469.764us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3242.050s 18636.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 181.370s 2862.498us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.960s 10.280us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 4.960s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 124.060s 3059.368us 1 1 100.00
chip_sw_otp_ctrl_descrambling 243.270s 3397.494us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 238.790s 3844.237us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.234s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 281.710s 3563.800us 1 1 100.00
ate_bootstrap_flash_erase 602.430s 10010.140us 0 1 0.00
ate_bootstrap_one_frame 6937.360s 45398.868us 1 1 100.00
ate_bootstrap_disjoint 10200.850s 85409.631us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 79164116220929644190769950260080506187855519973695080179843193768445877289465 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 44341001459345928659573129642562866637591695797601388331774743195357863949102 None
---- STDERR ----
Another command (pid=373201) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 64090776444885445574387480649209630293946088569010222098740257930519616927275 None
Another command (pid=597520) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=604182) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=619173) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 17275157752205182730718509332436501101206902860931340676575597786567799440291 None
---- STDERR ----
Another command (pid=601614) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 112433040015557342234922121575988052135879427764002961681695313117694123710956 None
Another command (pid=594907) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=585966) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=582078) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 42552343633842469716038097060872009260039875403753832822334576731674080960451 None
Another command (pid=648001) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=674149) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=676752) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 99517436372427809764033623033581068347813053719858367212752682716916000904805 None
Another command (pid=373201) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=421927) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=455093) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 23615079025292983189679336984762082402314384860603794936616835617008945187507 None
Another command (pid=619173) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=623133) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=585966) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 71943183803351236023148061554400768826867407771660340562505543959384479906586 None
Another command (pid=617431) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=560898) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=554756) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 60855356817366728922822266852630122241445205475160106979741139069740185983332 None
Another command (pid=554104) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=571707) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=570690) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 62935140984480543117455923091578725573513862377954584330107105153068560950327 None
Another command (pid=569148) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=640133) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=634123) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 50449944522061997025622194430222089943680513611739061524872458389831114602235 None
Another command (pid=556903) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=504227) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=558641) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 109448637437850521339287294259656566817684405304828752614677811088120265670565 None
---- STDERR ----
Another command (pid=558641) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=555843) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 62878068995888452567875828077549266294970959941174966191298082319571225142041 None
Another command (pid=624763) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=649698) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=652943) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 49134135529896723326512095967524691252547935488706120223448818607055615864252 None
Another command (pid=635461) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=651980) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=459807) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 48940762951777392539054792005821052109872211279052351693600008215936097069856 None
Another command (pid=599813) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=569643) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=601614) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 83025807629945355106591202175012102495975283718982096457070744707099078568465 None
---- STDERR ----
Another command (pid=373201) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 99250343990347421842624653991099309109564342173245381560067550899616454279001 None
Another command (pid=555381) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=460143) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=568663) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 21731623995427687911048984206814794447641420846648939876874037363566209679518 None
Another command (pid=455747) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=556903) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=504227) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 22044783743633085916499117731323550518309128558412166045379503552706972681593 None
Another command (pid=458959) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=473846) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=442017) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 95258895261630781694852104307639317722803432799132834138673644345170421582058 None
Another command (pid=387980) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=446535) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=443888) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 18162712974755847513158194139532730227390529959267263461428438910349496619417 None
Another command (pid=373201) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=400980) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=421927) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 91980061700257266186437713744673595786970585540205531913008675723205715707345 None
Another command (pid=751570) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=712009) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=677816) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 64272220455623990261188758692486148628050039757809106066979054627913201145373 None
Another command (pid=414281) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=421927) is running. Waiting for it to complete on the server (server_pid=274185)...
Another command (pid=455093) is running. Waiting for it to complete on the server (server_pid=274185)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 62499790769864108875793717686803841244009722555300775448673483223417908095723 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 86537044080791377881957854792030841676129283942109428266943717966917967123469 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 93642125979891943401139494279538610701122319417860462589143908987184908082121 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 108387692609280326798993898965463085532521822301504932334946965571133565793499 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 4406320992582869890979412297169255230696188376581628673968612320729112756086 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 28184394782405305198108308496435289394391374926461265546949043031838912292945 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 53797630364774935204866918945853981235469041772585710025753624185735042482597 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 109563079773703682823930166133155508811215881768476961047086638592410505163037 368
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 92765405488288830568533251456158984179628315707372800204757785469702548740367 368
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 23858171855917500849736377795688446792862906351181585538366793740309718736947 366
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 36936085849789771292872960176961372169328605945646663642898743433400430383301 326
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 27679222455393317170837403103144306988732737367793212193671823272399581361627 325
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 14820844571782274240085749595472419955252924929072202208888129707575450597317 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 29396671627446302125728109731985261984980230359517523518322318111084559896697 369
UVM_INFO @ 9791.699632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 60477742901694725458402235058405960161513294284560355093219742854445502311104 369
UVM_INFO @ 10621.785944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 36955460238033162386454074507136772762782195755850176628042290852867625944758 341
UVM_INFO @ 5611.356560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18746435663737942427056342225428645501644195782947843150920192988273728742025 327
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 60399950616327964154456335257754013578554428448047598513697791619548208703102 325
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 47319052426632665441743551861669121182055988203137784395739882868214728526322 328
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 79762283387408308706494400977316229227020444220823712873239730025730662824411 316
UVM_ERROR @ 2671.162514 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2671.162514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 113995938067927391620872235930006299670692051796301136929315073526608843087933 312
UVM_ERROR @ 3464.974282 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3464.974282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 2 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 113652760127328037858516601084124588646363381404081770637055860155297108444042 344
UVM_ERROR @ 11753.363000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11753.363000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 106214441426780451573842759389575450080280946460829591462077723024722297979538 319
UVM_ERROR @ 7433.768000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7433.768000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 87557317982667098034891507434073726212882525259007525152608335948213644977668 381
UVM_INFO @ 12026.757466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 99787714640269706152298715504377907661890688032727673816735799242179570331180 336
UVM_INFO @ 20018.653184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 100812589843612641091079081007447615328486359933346355380850459703352037873130 217
TL item was: req: (cip_tl_seq_item@31260) { a_addr: 'h104e8 a_data: 'h7d5f5697 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h181a2 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2185.891930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 62590395402086819146733899256509011806670029352474936937896973043698316349102 224
TL item was: req: (cip_tl_seq_item@31328) { a_addr: 'h104d8 a_data: 'h74d64260 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1bdb9 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2109.854477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 69271024617251507430117692305808883912758255803065509453528906705420810758764 365
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 23059480144363853286833568324793031732629351167878406490852977169181006594080 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 21563197490097577563752757767626125985301543159459365272087946678579793723191 368
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 2820261555260103735116364845352577482425545500849485496255855513004103687257 327
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 51676717355912393576428964324707186857115839530551210486414018026876628543474 301
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 14588276192566792678768761331307001200055709345313832391523911670967311320439 329
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 90664761474535005514713507756525535986867656319635377034978863278680109881581 309
UVM_INFO @ 3239.541080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 42915823128825873877842817981033263532253825807995287349092379190088116682971 342
UVM_INFO @ 6382.345936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 7816262324958877295299556247767032249604676631901872224667129862310400736246 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_prodend 60732794786937828124073494626437445464671455764397958495011995238690970068536 308
UVM_INFO @ 26501.722567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 51145110469882289065028786829492056434796504053043560723883583141205291595092 303
UVM_ERROR @ 2601.913912 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2601.913912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 3601125414550958054419873774625083213460323692425163675996060912846178427567 313
UVM_ERROR @ 2846.037335 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2846.037335 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 31606453534365152524127323261537069048435654749998995841963654246727045224355 332
UVM_INFO @ 34636.604101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:302)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 47242798911054873476055689331125280181397806126896407424972097683487142815581 307
UVM_INFO @ 3231.901152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 11717378826153035203550145384416947146440405328232100196307480622852223584024 308
UVM_INFO @ 2771.637760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 25555114960053530748164404092149965418323062577269960719026608600861867414099 None
Offending '(reset_cause == HwReq)' 1 test run
chip_sw_sensor_ctrl_alert 65632456775606011991802048271893162708317178073090165269126260903612606913571 331
UVM_ERROR @ 5454.169796 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 5454.169796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 55828377658434857903680036825069896799723728509698076058442088336064735575514 343
UVM_INFO @ 4388.942843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 38698307963516290395014498387283411694933584916673759264453849400403339426588 331
UVM_INFO @ 2658.274664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 97696037529140863998434521292351622613661426303294238341195338014774711311890 312
UVM_INFO @ 2711.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 57247451571520739634834413242724597333433879975705187107257948134385895786978 318
UVM_INFO @ 3811.208000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 98916046851678630121127071368251169096002644785787968165467078923619951446517 327
UVM_INFO @ 11975.918101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 72674805458723832293505075726976644079890934264664743874450809316962825988227 272
UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 60243337534311091924804721068103683588103944037005347549342522863727047644528 325
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 81274396084574217105245646034540554497364307789571936327995369330298371773053 327
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 62554052848364711202366015859566448880611897570657424129155003885864094599089 319
UVM_INFO @ 17813.187672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 51535083124424307380347682081659202993341671838810605030065416574557072659695 327
UVM_ERROR @ 4080.965608 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4080.965608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---